KEYWORDS: Neurons, Neural networks, Field programmable gate arrays, Silicon, Computer simulations, Telecommunications, Control systems, Analog electronics, Signal processing, Process modeling
Biological neural networks are based upon axonal point-to-point connections which inspire connectionist architecture.
As we attempt to engineer ever larger analogues of these neural networks we are forced to multiplex neural signals over
time shared paths. This can alter timing of neural information, which is critical in real-time oscillatory networks. Because
shared paths induce extra delay due to multiplexing signals, traveling on the channel and passing through routing
devices, guaranteeing event arrival deadlines across the communication process becomes crucial. This paper addresses
issues related to the guarantee of event timings with arbitrary deadline constraints in real-time distributed spiking neural
network systems based on token-ring architecture. To achieve this objective, we propose an integrated method in
selecting key system parameters. We show that several parameters must be set carefully if event deadlines are to be
satisfied. The token holding time (THT) parameter controls the bandwidth allocation for each node in the token-ring
network, and must be set properly to avoid deadline misses. The target token rotation time (TTRT) determines both the
speed of token circulation and the network utilization available to nodes. TTRT should also be chosen carefully to ensure
that the token circulates fast enough while maintaining a high available utilization. As prove of concept, the proposed
method is applied to a multi-board spiking neural network system hosting up to 140 analog neurons spread across 7
circuit-boards. Experimental analysis shows that deadline constraints are guaranteed along with bandwidth allocation
fairness when applying the proposed method.
The design flow of Analog and Mixed Signal has to be improved. In a specific application, we propose a definition of the
IP content and the structure of an IP-based library. The case study consists in the neuron-level integration of a complete
system that emulates spiking neural networks. As it is often the case, the development of the analog part of the system
requires the largest amount of time, due to the lack of formalism and automation in that domain. One solution to
accelerate the analog design cycle is to re-use already designed blocks and accumulated design knowledge, which could
be illustrated by the IP (Intellectual Property) concept. Indeed, an experience of about ten years and 19 designed ASICs
allow now to have an accurate idea of the system hierarchy and the recurrent analog blocks, which is the basis of IP-based
design. We will describe the IP-based library which has been developed for that specific application domain and
show how it can be used to accelerate the design cycle of the next ASIC generation.
This paper proposes a CMOS resizing methodology for analog circuits during a technology migration. The scaling rules
aim to be easy to apply and are based on the simplest MOS transistor model. The principle is to transpose one circuit
topology from one technology to another, while keeping the main figures of merit, and the issue is to quickly calculate
the new transistor dimensions. Furthermore, when the target technology has smaller minimum length, we expect to
obtain a decrease of area. This methodology is applied to both linear and non-linear examples: an OTA and a ring
oscillator. The results are compared on three CMOS processes whose minimum length is 0.8 μm, 0.35 μm, 0.25 μm.
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