As semiconductor wafer process technology advances, there is a notable miniaturization of complementary metal-oxide-semiconductor transistors, allowing for a higher transistor density on the predominant 12-in. silicon wafers. Despite this trend, a significant number of applications remain tethered to legacy wafer sizes such as 8 in., 6 in., or even smaller. Economically packaging these devices presents a challenge. Furthermore, many of these applications necessitate that the active surface remains exposed to external environments, contrasting with conventional packaging methods that shield the active surface with epoxy molding compounds. Addressing these specialized needs, we introduce a “chip-first face-up wafer-level fan-out packaging.” This innovative approach ensures that the active surface remains outward-facing and accessible for intended interactions with the environment while concurrently enabling electrical connections from the chip to the board on the side opposite to the active surface through the meticulous combination of redistribution layers and through-silicon vias.
The IC assembly industry has gone a full circle over the course of 50 years. At the beginning, everything was discretely packaged, but with the introduction of integrated circuits and advancement of lithograph y technologies, we were able to keep putting more into less., Yet the industry is facing challenges in continuing the scaling trend without sacrificing th e economic gain, therefore they turned to the heterogeneous integration, where the different IP blocks on the SOC were, once again, split into several discrete IC chips, thereby completing the circle. How do we enable these physically separated chips to have a performance that is on par with a single SOC? The answer is advanced packaging.
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