With the adoption of extreme ultraviolet (EUV) lithography for high-volume production of advanced nodes, stochastic variability and resulting failures, both post litho and post etch, have drawn increasing attention. There is a strong need for accurate models for stochastic edge placement error (SEPE) with a direct link to the induced stochastic failure probability (FP). Additionally, to prevent stochastic failure from occurring on wafers, a holistic stochastic-aware computational lithography suite of products is needed, such as stochastic-aware mask source optimization (SMO), stochastic-aware optical proximity correction (OPC), stochastic-aware lithography manufacturability check (LMC), and stochastic-aware process optimization and characterization. In this paper, we will present a framework to model both SEPE and FP. This approach allows us to study the correlation between SEPE and FP systematically and paves the way to directly correlate SEPE and FP. Additionally, this paper will demonstrate that such a stochastic model can be used to optimize source and mask to significantly reduce SEPE, minimize FP, and improve stochastic-aware process window. The paper will also propose a flow to integrate the stochastic model in OPC to enhance the stochastic-aware process window and EUV manufacturability.
Driving down imaging-induced edge placement error (EPE) is a key enabler of semiconductor technology node scaling1-3. From the 5 nm node forward, stochastic edge placement error (SEPE) is predicted to become the biggest contributor to total edge placement error. Many previous studies have established that LER, LCDU, and similar variability measurements require corrections for metrology artifacts and noise as well as mask variability transfer to more accurately represent wafer-level stochastic variability. In this presentation, we will discuss SEPE band behavior based on a methodology that allows local extraction of SEPE from total measured local variability (LEPU) in a generalized way along 2D contours.
With the adoption of extreme ultraviolet (EUV) lithography for high volume production in the advanced wafer manufacturing fab, defects resulting from stochastic effects could be one of major yield killers and draw increasing interest from the industry. In this paper, we will present a flow, including stochastic edge placement error (SEPE) model calibration, pattern recognition and hot spot ranking from defect probability, to detect potential hot spot in the chip design. The prediction result shows a good match with the wafer inspection. HMI eP5 massive metrology and contour analysis were used to extract wafer statistical edge placement distribution data.
Classical SEM metrology, CD-SEM, uses low data rate and extensive frame-averaging technique to achieve high-quality SEM imaging for high-precision metrology. The drawbacks include prolonged data collection time and larger photoresist shrinkage due to excess electron dosage. This paper will introduce a novel e-beam metrology system based on a high data rate, large probe current, and ultra-low noise electron optics design. At the same level of metrology precision, this high speed e-beam metrology system could significantly shorten data collection time and reduce electron dosage. In this work, the data collection speed is higher than 7,000 images per hr. Moreover, a novel large field of view (LFOV) capability at high resolution was enabled by an advanced electron deflection system design. The area coverage by LFOV is >100x larger than classical SEM. Superior metrology precision throughout the whole image has been achieved, and high quality metrology data could be extracted from full field. This new capability on metrology will further improve metrology data collection speed to support the need for large volume of metrology data from OPC model calibration of next generation technology. The shrinking EPE (Edge Placement Error) budget places more stringent requirement on OPC model accuracy, which is increasingly limited by metrology errors. In the current practice of metrology data collection and data processing to model calibration flow, CD-SEM throughput becomes a bottleneck that limits the amount of metrology measurements available for OPC model calibration, impacting pattern coverage and model accuracy especially for 2D pattern prediction. To address the trade-off in metrology sampling and model accuracy constrained by the cycle time requirement, this paper employs the high speed e-beam metrology system and a new computational software solution to take full advantage of the large volume data and significantly reduce both systematic and random metrology errors. The new computational software enables users to generate large quantity of highly accurate EP (Edge Placement) gauges and significantly improve design pattern coverage with up to 5X gain in model prediction accuracy on complex 2D patterns. Overall, this work showed >2x improvement in OPC model accuracy at a faster model turn-around time.
The extension of optical lithography to 7 nm node and beyond relies heavily on multiple litho-etch patterning technologies. The etch processes in multiple patterning often require progressively large bias differences between litho and etch as the target features become smaller. Moreover, since this litho-etch bias has strong pattern dependency, it must be taken into consideration during the Optical Proximity Correction (OPC) processes. Traditionally, two approaches are used to compensate etch biases: rule-based retargeting and model-based retargeting. The rule-based approach has a turn-around-time advantage but now has challenges meeting the increasingly tighter critical dimension (CD) requirements using a reasonable etch-bias table, especially for complex 2D patterns. Alternatively, model-based retargeting can meet these CD requirements by capturing the etch process physics with high accuracy, including the etch bias variability that arises from both patterning proximity effects and etch chamber non-uniformity. In the past, empirical terms have been used to approximate the etch bias due to pattern proximity effects but sometimes empirical models are known to have compromised model accuracy so a physical based approach is desired. This paper’s work will address the etch bias variability due to patterning proximity effects by using a physical approach based simplified chemical kinetics. It starts from a well calibrated After-Development-Inspection (ADI) model and the subsequent etch model is based on the ADI model contour. By assuming that plasma chemical species in the trenches are maintained in an equilibrium state, the plasma species act on the edges to induce etch bias. Methods are developed to evaluate plasma collision probability on trench edges for random layouts. Furthermore, the impact of resist materials on etch bias are treated with Arrhenius equation or as a second order reaction. Equations governing plasma collision probabilities on trench edges as a function of time are derived. An etch bias model can be calibrated based on those equations. Experimental results have shown that this physical approach to model etch bias is a promising direction to applications for full-chip etch proximity corrections.
KEYWORDS: Extreme ultraviolet, Data modeling, Photomasks, Scattering, Monte Carlo methods, Point spread functions, Process modeling, Electron beams, Tantalum, Chromium
In electron beam writing on EUV mask, it has been reported that CD linearity does not show simple signatures as
observed with conventional COG (Cr on Glass) masks because they are caused by scattered electrons form EUV mask
itself which comprises stacked heavy metals and thick multi-layers. To resolve this issue, Mask Process Correction
(MPC) will be ideally applicable. Every pattern is reshaped in MPC. Therefore, the number of shots would not increase
and writing time will be kept within reasonable range. In this paper, MPC is extended to modeling for correction of CD
linearity errors on EUV mask. And its effectiveness is verified with simulations and experiments through actual writing
test.
In order to support complex optical masks today and EUV masks in the near future, it is critical to correct mask
patterning errors with a magnitude of up to 20nm over a range of 2000nm at mask scale caused by short range mask
process proximity effects. A new mask process correction technology, MPC+, has been developed to achieve the target
requirements for the next generation node. In this paper, the accuracy and throughput performance of MPC+ technology
is evaluated using the most advanced mask writing tool, the EBM-70001), and high quality mask metrology .
The accuracy of MPC+ is achieved by using a new comprehensive mask model. The results of through-pitch and
through-linewidth linearity curves and error statistics for multiple pattern layouts (including both 1D and 2D patterns)
are demonstrated and show post-correction accuracy of 2.34nm 3σ for through-pitch/through-linewidth linearity.
Implementing faster mask model simulation and more efficient correction recipes; full mask area (100cm2) processing
run time is less than 7 hours for 32nm half-pitch technology node.
From these results, it can be concluded that MPC+ with its higher precision and speed is a practical technology for the
32nm node and future technology generations, including EUV, when used with advance mask writing processes like the
EBM-7000.
We report the development of Mask-LMC for defect printability evaluation from sub-200nm wavelength mask
inspection images. Both transmitted and reflected images are utilized, and both die-to-die and die-to-database inspection
modes are supported. The first step of the process is to recover the patterns on the mask from high resolution T and R
images by de-convolving inspection optical effects. This step uses a mask reconstruction model, which is based on
rigorous Hopkins-modeling of the inspection optics, and is pre-determined before the full mask inspection. After mask
reconstruction, wafer scanner optics and wafer resist simulations are performed on the reconstructed mask, with a wafer
lithography model. This step leverages Brion's industry-proven, hardware-accelerated LMC (Lithography
Manufacturability Check) technology1. Existing litho process models that are in use for Brion's OPC+ and verification
products may be used for this simulation. In the final step, special detectors are used to compare simulation results on the
reference and defect dice. We have developed detectors for contact CD, contact area, line and space CD, and edge
placement errors. The detection results on test and production reticles have been validated with AIMSTM.
We report the development of Mask-LMC for defect printability evaluation from sub-200nm wavelength mask
inspection images. Both transmitted and reflected images are utilized, and both die-to-die and die-to-database inspection
modes are supported. The first step of the process is to recover the patterns on the mask from high resolution T and R
images by de-convolving inspection optical effects. This step uses a mask reconstruction model, which is based on
rigorous Hopkins-modeling of the inspection optics, and is pre-determined before the full mask inspection. After mask
reconstruction, wafer scanner optics and wafer resist simulations are performed on the reconstructed mask, with a wafer
lithography model. This step leverages Brion's industry-proven, hardware-accelerated LMC (Lithography
Manufacturability Check) technology1. Existing litho process models that are in use for Brion's OPC+ and verification
products may be used for this simulation. In the final step, special detectors are used to compare simulation results on the
reference and defect dice. We have developed detectors for contact CD, contact area, line and space CD, and edge
placement errors. The detection result has been validated with AIMSTM.
In the continuous battle to improve critical dimension (CD) uniformity, especially for 45-nanometer (nm) logic
advanced products, one important recent advance is the ability to accurately predict the mask CD uniformity
contribution to the overall global wafer CD error budget. In most wafer process simulation models, mask error
contribution is embedded in the optical and/or resist models. We have separated the mask effects, however, by
creating a short-range mask process model (MPM) for each unique mask process and a long-range CD
uniformity mask bias map (MBM) for each individual mask. By establishing a mask bias map, we are able to
incorporate the mask CD uniformity signature into our modelling simulations and measure the effects on global
wafer CD uniformity and hotspots. We also have examined several ways of proving the efficiency of this
approach, including the analysis of OPC hot spot signatures with and without the mask bias map (see Figure 1)
and by comparing the precision of the model contour prediction to wafer SEM images. In this paper we will
show the different steps of mask bias map generation and use for advanced 45nm logic node layers, along with
the current results of this new dynamic application to improve hot spot verification through Brion Technologies'
model-based mask verification loop.
The minimum feature size of integrated circuit continues to shrink. At 32 nm and smaller nodes, mask linearity
errors caused by short range proximity effects less than around 3um during the manufacturing of photomasks
become more significant in the overall lithography error budget. To address this, we have carried out a study that:
(1). models the short range mask error; (2). implements mask process correction (MPC) based on these mask error
models; and (3). verifies the mask process corrections. In this paper we will demonstrate that application of MPC
can significantly reduce mask errors with minimal increase in writing overhead.
This paper presents an interferometric method with high sensitivity and good linearity for calibration of micromirror arrays used in maskless lithography. An analytic model based on electric-field perturbation is developed to quantify the influences of mirror configuration and defocus on calibration sensitivity. With the analytic model, two optimization strategies to achieve the highest sensitivity are developed. For a 5-by-5 sub-array with a pixel size of 0.5λ/NA, the sensitivity is improved from 0.0078 I/° when the surrounding pixels are not actuated, to 0.02286 I/° and 0.0347 I/° when the pixels are arranged in optimized schemes at defocus of 0.0RU and 1.5RU, respectively. The typical improvement is about 3X to 4X when the optimized calibration schemes are used.
In this paper we present the design and fabrication results of tilting and piston micromirrors for their potential applications in DUV and EUV maskless lithography. The dynamic characteristics such as stability, damping, and the settling time of various types of electro-mechanically coupled micromirrors are investigated using the perturbation method, linear control theory, and numerical simulation. Non-dimensional control parameters are identified and transient optimization is carried out to minimize the systems’ settling time. It is found that vertical double-comb tilting micromirrors and clamped double-flexure piston micromirrors have superior stability.
The mirror hinge is proposed to function as a built-in resistor to introduce optimal electrical damping for EUV micromirrors operating in vacuum. We have developed a low-temperature (<420°C) IC compatible SiGe process, in which SiGe can be doped at different levels without annealing to function as a structural (conductive) and damping (resistive) material. Self-aligned processes using "spacer nanolithography" to define ultra-thin nano-scale actuation gaps for low-voltage operation have been developed to fabricate both tilting and piston micromirrors. We have successfully constructed double-comb tilting micromirrors with 300-nm fingers and 40-nm finger gaps, and double-flexure piston micromirrors with 80-nm thick flexures and 80-nm actuation gaps. The mirror sizes are in the range of 10 to 0.5 mm.
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