KEYWORDS: Modulation, Critical dimension metrology, Electron beam direct write lithography, Point spread functions, Electron beam lithography, Cadmium sulfide, Electron beams, Optical lithography, Manufacturing, Backscatter
After the successful results obtained in the last few years, electron beam direct write (EBDW) lithography for use in integrated circuit manufacturing has now been demonstrated. However, throughput and resolution capabilities need to be improved to push its interest for fast cycle production and advanced research and development applications. In this way, the process development needs good patterns dimensional accuracy, i.e., a better control of the proximity effects caused by backscattering electrons and others phenomenon. In this work, the limitations of the dose modulation method are investigated through the change of dose number steps and the use of a more accurate point spread function. To continue reducing feature sizes, a method to provide a complementary correction to the dose modulation solution is proposed. This rule-based electron beam proximity correction, or REBPC, provides good results down to 40 nm.
With the strong increase of mask complexity and associated price for each new technology node, mask less lithography represents more and more an interesting and complementary alternative for ASIC manufacturing especially in the fields of low volume and leading eadge technology applications. In the semiconductor business where prices and cycle time are constantly pressured, the capability and flexibility of the electron beam direct write offer an effective real cost and cycle time opportunity thanks to its high-resolution capability but also to its ability to print, modify or correct design everywhere in a circuit. This paper highlights application examples where the advantages of this lithography solution are demonstrated for advanced research and development application with the patterning of 45 nm SRAM and for the fast validation of architecture designs. This work confirms that mask less lithography can be transparently placed into production environment, in association with the "golden" optical lithography reference.
KEYWORDS: Line width roughness, Electron beam direct write lithography, Semiconducting wafers, Electron beam lithography, Electron beams, Manufacturing, Etching, Photoresist processing, Coating, Semiconductors
Electron Beam Direct Write (EBDW) lithography represents a low cost and a rapid way to start basic studies for advance devices and process developments. Patterning for sub-45nm node technology requires the development of high performance processes. Different alternatives for the improvement of EBDW lithography are investigated in this paper for the ASIC manufacturing on 300mm wafer size. Among them, process development has been tuned for clear field equivalent level to improve both line width roughness by monitoring post applied bake conditions, and both process window by specific design correction. Concerning dark field level, process resolution has been improved by a shrinkage technique.
Laurent Pain, M. Jurdit, Yves LaPlanche, J. Todeschini, Serdar Manakli, G. Bervin, Ramiro Palla, A. Beverina, R. Faure, X. Bossy, H. Leininger, S. Tourniol, M. Broekaart, F. Judong, K. Brosselin, P. Gouraud, Veronique De Jonghe, Daniel Henry, M. Woo, Peter Stolk, B. Tavel, F. Arnaud
The introduction of Electron Beam Direct Write lithography into production represents a
challenging alternative to reduce cost and cycle time increase induced by the introduction of new
generation nodes. This paper details the development work performed to insert transparently direct
write lithography process and alignment strategies into CMOS process flows. Finally, this
interchangeability between E-Beam and optical lithography steps offers a complete flexibility for
device architecture validation and allowed the development of a complete low cost 65nm platform
including low-power and general-purpose applications.
An easy way to pattern 65nm CD target, when optical lithography technology is not available, is to use an Electron Beam Direct Write tool (EBDW), which is well known for its high resolution patterning potentials, with the drawback of a very low throughput. Emerging techniques of electron projection lithography also propose the same patterning capability with enhanced throughput. One of the most crucial issues, when dealing with integration, is the overlay capability of the systems. This paper exposes the studies made on the overlay capability issue of the LEICA EBDW installed in STMicroelectronics (STM) production plant in Crolles (France) and proves our tool is ready to support the 65nm node technology development.
With the objective to ramp-up 65 nm CMOS production in early 2005, preliminary works have to start today to develop the basic technological in order to be correctly prepared. In the absence of commercial advanced 193 nm scanners compatible with these aggressive design rules, electron beam technology was employed for the realization of a first 6-T SRAM cell of a size of 0.69 μm2. This paper highlights the work performed to integrate E-beam lithography in this first 65 nm CMOS process flow.
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