Pulse Coupled Neural Networks are a very useful tool for image processing and visual applications, since it has the
advantages of being invariant to image changes as rotation, scale, or certain distortion. Among other characteristics, the
PCNN changes a given image input into a temporal representation which can be easily later analyzed for pattern
recognition. The structure of a PCNN though, makes it necessary to determine all of its parameters very carefully in
order to function optimally, so that the responses to the kind of inputs it will be subjected are clearly discriminated
allowing for an easy and fast post-processing yielding useful results. This tweaking of the system is a taxing process.
In this paper we analyze and compare two methods for modeling PCNNs. A purely mathematical model is programmed
and a similar circuital model is also designed. Both are then used to determine the optimal values of the several
parameters of a PCNN: gain, threshold, time constants for feed-in and threshold and linking leading to an optimal design
for image recognition. The results are compared for usefulness, accuracy and speed, as well as the performance and time
requirements for fast and easy design, thus providing a tool for future ease of management of a PCNN for different tasks.
Support Vector Machines are currently one of the best classification algorithms used in a wide number of applications.
The ability to extract a classification function from a limited number of learning examples keeping in the structural risk
low has demonstrated to be a clear alternative to other neural networks.
However, the calculations involved in computing the kernel and the repetition of the process for all support vectors in the
classification problem are certainly intensive, requiring time or power consumption in order to function correctly. This
problem could be a drawback in certain applications with limited resources or time. Therefore simple algorithms
circumventing this problem are needed.
In this paper we analyze an FPGA implementation of a SVM which uses a CORDIC algorithm for simplifying the
calculation of as specific kernel greatly reducing the time and hardware requirements needed for the classification,
allowing for powerful in-field portable applications. The algorithm is and its calculation capabilities are shown. The full
SVM classifier using this algorithm is implemented in an FPGA and its in-field use assessed for high speed low power
classification.
In this paper we provide a simple and fast hardware implementation for a Support Vector Machine (SVM). By using the
CORDIC algorithm and implementing a 2-based exponential kernel that allows us to simplify operations, we overcome
the problems caused by too many internal multiplications found in the classification process, both while applying the
Kernel formula and later on multiplying by the weights. We show a simple example of classification with the algorithm
and analyze the classification speed and accuracy.
In this paper we address the problem of Support Vector Machine (SVM) learning. We describe an analogue
implementation for a Sequential Minimal Optimization (SMO) algorithm to simplify the hardware requisites of
the learning phase. The advantages from a full set training circuit are shown and a test is carried out on a simple case to prove its effectiveness.
Support vector machines (SVM) present very interesting features in the field of image processing, but the intensive
calculation needed complicates its use in real-time applications. We present an architecture for a SVM which simplifies
most of the calculus using an optoelectronic matrix-vector multiplier (OMVM).
In this paper we present the scheme for a control circuit used in an image processing system which is to be
implemented in a neural network which has a high level of connectivity and reconfiguration of neurons for integration
and trigger based on the Address-Event Representation. This scheme will be employed as a pre-processing stage for a
vision system which employs as its core processing an Optical Broadcast Neural Network (OBNN). [Optical
Engineering letters 42 (9), 2488(2003)]. The proposed vision system allows the possibility to introduce patterns from
any acquisition system of images, for posterior processing.
In this paper we investigate a hardware Pulse Couple Neural Network (PCNN) to be used as the pre-processing stage for a vision system which uses as processing core the Optical Broadcast Neural Network (OBNN) Processor [Optical Engineering Letters 42 (9), 2488 (2003)]. The temporal patterns are to remain constant independently of the position of the spatial pattern in the input image and its orientation. The objective is to obtain synchronous temporal patterns, with fixed pulse rates, from a determined spatial pattern.
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