To reduce the pattern size in photomask is an inevitable trend because of the minimization of chip size. So it makes a big challenge to control defects in photomask industry. Defects below a certain size that had not been any problem in previous technology node are becoming an issue as the patterns are smaller. Therefore, the acceptable tolerance levels for current defect size and quantity are dramatically reduced. Because these defects on photomask can be the sources of the repeating defects on wafer, small size defects smaller than 200nm should not be ignored any more. Generally, almost defects are generated during develop process and etch process. Especially it is difficult to find the root cause of defects formed during the develop process because of their various types and very small size. In this paper, we studied how these small defects can be eliminated by analyzing the defects and tuning the develop process. There are 3 types of resist defects which are named as follows. The first type is ‘Popcorn’ defect which is mainly occurred in negative resist and exists on the dark features. The second type is ‘Frog eggs’ defect which is occurred in 2nd process of HTPSM and exists on the wide space area. The last type is ‘Spot’ defect which also exists on the wide space area. These defects are generally appeared on the entire area of a plate and the number of these defects is about several hundred. It is thought that the original source is the surface’s hydrophilic state before develop process or the incongruity between resist and developer. This study shows that the optimizing the develop process can be a good solution for some resist defects.
As EUV(Extreme Ultraviolet) Lithography has been delayed because of technical difficulties, ArF-immersion
technology is continued to be utilized in the several future years. To progress constantly chip’s minimization and pattern shrink with ArF wavelength, the adoption of aggressive SRAF(Sub Resolution Assist Feature) is inevitable. This trend is giving the big challenge in Photomask industry such as pattern collapse, pattern wiggling and bending. Generally, the reduction of the resist thickness is being tried to solve these problems. But this approach has the limitation, because of
depending on the margin of etch process. Additionally, finding appropriate resist must be evaluated by a variety of experiments for verifying the stability of the process. According to several papers, the main reason of pattern collapse is
the unbalanced capillary force at drying step in develop process. The capillary stresses (σ) experienced by the resist can
be described as shown in equation (1.1) and Figure 1[1].
The acceptable tolerance level for CD signatures induced by any process step in the mask manufacturing process has
been dramatically reduced with each technology node. Chemical amplified resists (CAR) are used extensively for first layer mask imaging. Therefor a post exposure bake (PEB) process is required after resist exposure, adding yet another potential source of CD signatures. Consequentially, the thermal imprint of the bake process must be further reduced to meet the requirements of future technology nodes.
The influence of the measurement devices (wireless and wired sensor arrays) used to optimize the hotplate, on the performance of the Post Exposure Bake (PEB) process is discussed in [1,2]. A concept of utilizing two wired sensor arrays, with wire connections attached in opposite locations on the sensor array surface, called “Mirror Bake” is introduced. Based on the individual hotplate optimization for each of those two sensor arrays, a combined bake recipe for the multi-zone hotplate is calculated. This method eliminates the systematic temperature non-uniformity introduced by the sensor array hardware, when optimizing the recipes with only one sensor array.
In this paper the “mirror bake” concept is validated by comparing the CD uniformity data of masks manufactured with a PEB process, optimized using a single standard sensor array vs. the “mirror bake” concept. The “mirror bake” concept achieved a CD uniformity improvement of up to 30% (CD range). During this work additional hardware influences from the sensor arrays were identified.
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