An ultra-compact 1.31μm-emission photonic crystal (PC) nano-ridge laser directly grown on a silicon substrate without thick buffer layers achieves lasing with a cavity length as small as 50 μm at a remarkably low pumping threshold of 4.42 kW/cm2. This laser exhibits a lasing peak with side-mode suppression ratio of over 17 dB and a linewidth as narrow as 1.47 nm under 22.91 kW/cm2 pulsed pumping.
We demonstrate the co-integration of SiN waveguide-based building block components in an established 200 mm Silicon photonics platform, extending its capabilities to the 1 µm wavelength range, and addressing bioimaging applications based on Optical Coherence Tomography (OCT). Measured coupling and propagation loss, at wafer-scale, are low for edge couplers (< 2 dB), and PECVD SiN waveguides (< 0.4 dB/cm) respectively. SiN waveguide-coupled Ge-on-Si photodetectors with 0.6 A/W responsivity at 1060 nm and dark currents lower than 15 nA at -1 V operating voltage were achieved at wafer-scale, with a smaller footprint compared to standard Si-based photodetectors. This platform has the potential to be used for a variety of applications, such as optical communications, imaging, and sensing. The achieved results at 1060 nm pave the way for the deployment of miniaturized OCT-based devices to enable large scale patient diagnosis.
Co-packaged optics for high performance computing or other data center applications requires dense integration of silicon photonic integrated circuits (PICs) with electronic integrated circuits (EICs). This work discusses the impact of three-dimensional (3D) hybrid integration on the thermal performance of Si ring-based photonic devices in wavelength-division multiplexing PICs. A thermal finite element model of the EIC-PIC assembly is developed and calibrated with thermo-optic device measurements, before and after integration of an electrical driver on top of the PIC by means of microbump flip-chip bonding. Both measurements and simulations of the thermal tuning efficiency and crosstalk between silicon photonic devices show that the EIC can have a significant impact on the thermal performance of the integrated heaters in the PIC by acting as an undesired heat spreader. This heat spreading lowers the heater efficiency with 43.3% and increases the thermal crosstalk between the devices by up to 44.4% compared with a PIC-only case. Finally, it is shown that these negative thermal effects of 3D integration can largely be mitigated by a thermally aware design of the microbump array and the back-end-of-line interconnect, guided by the calibrated thermal simulation model.
Graphene-based devices have garnered significant attention for their potential in numerous applications, notably in integrated photonics. For graphene devices to be used in real-world systems, it is necessary to demonstrate competitive device performance, repeatability of results, reliability, and a path to large-scale manufacturing with high yield at low cost. In this study, single-layer graphene electro-absorption modulators serve as a pivotal test vehicle to facilitate wafer-scale integration in a 300mm pilot CMOS foundry, harnessing imec silicon photonics platforms along with the 6- inch graphene transfer capabilities of Graphenea. The patterning of graphene is achieved utilizing a hardmask, with tungsten-based contacts being developed via the damascene method to facilitate CMOS-compatible manufacturing. Through an extensive analysis of inline metrology data during process development along with analysis of hundreds of devices on each wafer, the impact of specific processing steps on the performance could be identified and optimized. Subsequent to optimization, a modulation depth of 50 ± 4 dB/mm is exemplified across 400 devices, measured utilizing 5 V peak-to-peak voltage, achieving electro-optical bandwidths up to 15.1 ± 1.8 GHz for 25μm-long devices. The results achieved are comparable to lab-based record-setting graphene devices of similar design and chemical vapor deposition graphene quality. By demonstrating the reproducibility of the results across hundreds of devices, this work resolves the bottleneck of graphene wafer-scale integration. Furthermore, CMOS-compatible processing enables co-integration of graphene-based devices with other photonics and electronics building blocks on the same chip, and for high-volume low-cost manufacturing.
Silicon photonics is now considered the photonics platform of choice for short-reach data center single mode pluggable transceivers. With the emergence of co-packaged optics concepts, it can also enable high performance computing with power-efficient interconnect, but also Lidar system integration or even optical quantum computing. In this paper we will present an overview of what can be achieved in state-of-the-art silicon photonics platforms and we will discuss some of the emerging technology trends. In particular, we will discuss the integration of LPCVD SiN in an active silicon photonics platform.
This paper presents the necessary building blocks towards the realization of on-chip, lens-free, spectrally selective, THz beam steering. We demonstrate continuous wave (CW) THz generation up to 2.2 THz by photomixing using antenna-coupled silicon-integrated germanium photodiodes, which reach an optical-to-THz conversion efficiency of about 1% at 100 GHz. We show THz beam forming within a small antenna array and address key challenges towards the realization of large quasi-optical THz phased arrays, by demonstrating low-loss (<0.2 dB/cm), low phase error routing and optical beam steering within hybrid Si/SiN optical phased arrays. Finally, we present an anti-reflection structure enabling lensfree THz beam steering.
Micro-transfer-printing (µTP) enables the intimate integration of diverse non-inherent functionalities on a target substrate and hence allows for the realization of complex photonic integrated circuits (PICs) with small footprint. By employing a polydimethylsiloxane (PDMS) elastomeric stamp with an array of posts, a large number of micro-components can be integrated on a target wafer in one transfer printing operation, which leads to substantial cost reduction of the resulting PICs. This paper discusses the use of µTP for the realization of III-V lasers on Si and SiN PICs and summarizes the recent progress that has been made in this field.
High-speed electronic integrated circuits are essential to the development of new fiber-optic communication systems. As a consequence of the increasing speeds and multi-channel operation, close integration and co-design of photonic and electronic devices have become a necessity to realize high-performance sub-systems. Such co-design on the other hand also enables the design of new electro-optic architectures to create and process multi-level optical signals. This presentation will illustrate a number of recent and ongoing developments in IDLab, an imec research group, from various H2020 projects with a focus on application-specific high-speed electronic transceiver circuits such as driver amplifiers and transimpedance amplifiers (TIAs).
The silicon photonics platform is still missing a native source. Therefore, using a novel epitaxial process based on aspect ratio trapping and nano-ridge engineering we demonstrated an powerfull approach to fabricate GaAs-InGaAs lasers directly on a standard silicon substrate. In depth morphological and optical characterisation confirms the high quality of the material. We demonstrated lasing from DFB-type devices with etched gratings and with metal gratings. In the presentation we will also discuss the possibility for coupling to standard silicon waveguides and for extending the emission to longer wavelengths.
The rapid increase of bandwidth requirements across the entire hierarchy of Data Center (DC) networks, ranging from chip-to-chip, board-to-board up to rack-to-rack communications, puts strenuous requirements in the underlying network infrastructure that has to offer high-bandwidth and low-latency interconnection under a low-energy and low-cost envelope. Arrayed Waveguide Grating Router (AWGR)-based optical interconnections have emerged as a powerful architectural framework that can overcome the currently deployed electrical interconnect bottlenecks leveraging the wavelength division multiplexing (WDM) and the cyclic routing properties of AWGRs to offer one-hop, all-to-all communication when employed as N×N routers. However, the majority of previous silicon (Si)-based integrated AWGR demonstrations has either targeted C-band operation, despite the dominance of the O-band spectral region in the DC interconnection domain, or offered coarse-WDM (CWDM) functionality and, as such, were limited in terms of AWGR port count. In this article, we present for the first time to our knowledge, a Dense-WDM (DWDM) 16×16 Si-photonic cyclic-frequency AWGR device targeting O-band routing applications. The fabricated AWGR device features a channel spacing of 1.063 nm (189 GHz), a free spectral range of 17.8 nm (3.15 THz) and a 3-dB bandwidth of 0.655 nm (116 GHz). Its proper cyclic frequency operation was experimentally verified for all 16 channels with channel peak insertion loss values in the range of 3.9 dB to 8.37 dB, yielding a channel loss non-uniformity of 4.47 dB. Its compact footprint of 0.27×0.71 mm2 and low crosstalk of 21.65 dB highlight its potential for employment in future AWGR-based interconnection schemes.
Terahertz (THz) imaging has progressed tremendously due the continuous development of new THz emitters and detectors. However, highly integrated array devices are desired for fast THz imaging. Advanced features such as beam steering and phase contrast imaging may be realized using more complex systems that require tight integration. Silicon photonics is an enabler for CW THz applications such as imaging and high-speed communication because of low cost and high level of integration. We present results of our research on continuous-wave THz generation using antennacoupled silicon-germanium photodiodes. THz emission up to 2.2 THz has been demonstrated.
Laser integration and photonics chip packaging are the two key challenges that require attention to drive down the cost/bit metric for silicon photonics based optical interconnects. We try to address the latter by demonstrating optical interfaces that fit well in an overall scheme of 2.5D/3D electro-optic integration needed for a high performance computing environment. A through-substrate coupling interface provides the benefit of bonding a silicon photonic chip face-up on a package substrate such that the device-side of the chip remains accessible for die-stacking and fiber-array packaging, thereby offering a promising alternative to flip-chip based packaging. In this paper, we demonstrate three through-substrate coupling elements to enable alignment tolerant and energy-efficient integration of silicon photonics with board-level or package-level optical interconnects : (i) a downward directionality O-band grating coupler with a peak -2.3 dB fiber-to-silicon waveguide coupling efficiency; (ii) polymer microlenses hybrid integrated onto the substrate of a silicon photonic chip to produce an expanded collimated beam at λ=1310 nm for a distance of more than 600 μm; (iii) a ball lens placed in a through-package via to result in a 14 μm chip-to-package 1-dB lateral alignment tolerance for coupling into a 20×24 µm squared cross-section board-level polymer waveguide.
Directly interfacing a photonic integrated circuit allows at best an alignment tolerance of a few micrometer due to the small dimensions of optical (coupling) features on chip, but when using microlenses integrated on the substrate-side, alignment tolerances for interfacing the chips can greatly be relaxed. This is demonstrated on a 750 μm thick chip with standard grating couplers (operation wavelength around 1550 nm). Low roughness silicon microlenses were realized by transferring reflowed photoresist into the silicon substrate using reactive ion etching. The microlens allows interfacing the chip from the backside with an expanded beam, drastically increasing lateral alignment tolerances. A 1 dB alignment tolerance of ±8 μm and ±11 μm (along and perpendicular to the grating coupler direction, respectively) was experimentally found when a 40 μm mode field diameter beam was used at the input.
Within the European Project TERABOARD, a photonic integration platforms including electronic-photonic integration is developed to demonstrate high bandwidth high-density modules and to demonstrate cost and energy cost target objectives. Large count high bandwidth density EO interfaces for onboard and intra-data center interconnection are reported. For onboard large count interconnections a novel concept based on optical-TSV interconnection platform with no intersections and no WDM multiplexing is reported. All input/output coupler arrays based on a pluggable silica platform are reported as well.
In this presentation we will report on our recent work on new materials that can be monolithically integrated on high-index contrast silicon or silicon nitride photonic ICs to enhance their functionality. This includes graphene and other 2D-materials for realizing compact electro-absorption modulators and non-linear devices, ferroelectric materials for realizing phase modulators and adiabatic couplers for realizing bistable switches.
In the paper, we elaborate our recent work on monolithic (by epitaxial growth) and heterogeneous (by adhesive bonding) integration techniques that may pave the path to the final solutions of IIIV lasers on silicon in different scenarios. In the case of on-chip optical interconnects, a large number of IIIV lasers with high integration density are highly demanded. By using a buffer-less selective growth technique, we are able to grow submicron-sized InP waveguides directly on silicon. All the dislocations are confined at the interface between Si and InP, which leads to the successful demonstration of a distributed feedback (DFB) laser array with good uniformity. Thanks to the minimized buffer layer thickness (20 nm) and the standard top-down laser process flow, it is possible to demonstrate very high integration density of IIIV lasers on silicon. Recently, by growing InGaAs/InP heterostructures on the virtual lattice-matched InP-on-Si template, we are able to achieve room-temperature lasing at communication wavelength range.
On the other hand, the relatively mature bonding based heterogeneous integration technology has been well developed over the last decade, and the integration of various laser configurations on silicon lead to more system level demonstrations. Here, we present our recent work on IIIV-on-Si mode-locked lasers. Thanks to the extremely low silicon waveguide loss, we are able to achieve record-low repetition rate of 1GHz, with an extremely low RF linewidth (sub-kHz). Such devices are promising for applications such as spectroscopy, microwave photonics etc.
Realization of a monolithically integrated on-chip laser source remains the holy-grail of Silicon Photonics. Germanium (Ge) is a promising semiconductor for lasing applications when highly doped with Phosphorous (P) and or alloyed with Sn [1, 2]. P doping makes Ge a pseudo-direct band gap material and the emitted wavelengths are compatible with fiber-optic communication applications. However, in-situ P doping with Ge2H6 precursor allows a maximum active P concentration of 6×1019 cm-3 [3]. Even with such active P levels, n++ Ge is still an indirect band gap material and could result in very high threshold current densities. In this work, we demonstrate P-doped Ge layers with active n-type doping beyond 1020 cm-3, grown using Ge2H6 and PH3 and subsequently laser annealed, targeting power-efficient on-chip laser sources.
The use of Ge2H6 precursors during the growth of P-doped Ge increases the active P concentration level to a record fully activated concentration of 1.3×1020 cm-3 when laser annealed with a fluence of 1.2 J/cm2. The material stack consisted of 200 nm thick P-doped Ge grown on an annealed 1 µm Ge buffer on Si. Ge:P epitaxy was performed with PH3 and Ge2H6 at 320oC. Low temperature growth enable Ge:P epitaxy far from thermodynamic equilibrium, resulting in an enhanced incorporation of P atoms [3]. At such high active P concentration, the n++ Ge layer is expected to be a pseudo-direct band gap material. The photoluminescence (PL) intensities for layers with highest active P concentration show an enhancement of 18× when compared to undoped Ge grown on Si as shown in Fig. 1 and Fig. 2. The layers were optically pumped with a 640 nm laser and an incident intensity of 410 mW/cm2. The PL was measured with a NIR spectrometer with a Hamamatsu R5509-72 NIR photomultiplier tube detector whose detectivity drops at 1620 nm. Due to high active P concentration, we expect band gap narrowing phenomena to push the PL peak to wavelengths beyond the detection limit (1620nm) of the setup. Therefore, the 18× enhancement is a lower limit estimation. In this contribution, an extensive study of laser annealing conditions and their impact on material properties will be discussed.
A major concern in using highly doped Ge as an active medium is the increase in free-carrier absorption (FCA). However, results reported in [4] suggest that FCA is significantly dominated by holes due to larger absorption cross-section of holes compared to electrons. The FCA results in [4] and JDOS modeling were used to calculate the gain spectrum for the highest doped Ge samples, including the typical 0.25% biaxial tensile strain of epitaxial Ge on Si. A carrier lifetime of 3 ns is required as shown in Fig. 3 for a target threshold current density of sub-20 kA/cm2 which represents at least tenfold reduction when compared to active P-doping level of 6×1019 cm-3. As a result, laser annealed highly doped Ge layers grown with Ge2H6 precursors are a promising approach for realizing a power efficient on-chip Ge laser source.
Silicon photonics has become in the past years an important technology adopted by a growing number of
industrial players to develop their next generation optical transceivers. However most of the technology
platforms established in CMOS fabrication lines are kept captive or open to only a restricted number of
customers. In order to make silicon photonics accessible to a large number of players several initiatives exist
around the world to develop open platforms. In this paper we will present imec’s silicon photonics active
platform accessible through multi-project wafer runs.
Large-scale photonics integration has been proposed for many years to support the ever increasing requirements for long and short distance communications as well as package-to-package interconnects. Amongst the various technology options, silicon photonics has imposed itself as a promising candidate, relying on CMOS fabrication processes. While silicon photonics can share the technology platform developed for advanced CMOS devices it has specific dimension control requirements. Though the device dimensions are in the order of the wavelength of light used, the tolerance allowed can be less than 1% for certain devices. Achieving this is a challenging task which requires advanced patterning techniques along with process control. Another challenge is identifying an overlapping process window for diverse pattern densities and orientations on a single layer. In this paper, we present key technology challenges faced when using optical lithography for silicon photonics and advantages of using the 193nm immersion lithography system. We report successful demonstration of a modified 28nm- STI-like patterning platform for silicon photonics in 300mm Silicon-On-Insulator wafer technology. By careful process design, within-wafer CD variation (1sigma) of <1% is achieved for both isolated (waveguides) and dense (grating) patterns in silicon. In addition to dimensional control, low sidewall roughness is a crucial to achieve low scattering loss in the waveguides. With this platform, optical propagation loss as low as ~0.7 dB/cm is achieved for high-confinement single mode waveguides (450x220nm). This is an improvement of >20 % from the best propagation loss reported for this cross-section fabricated using e-beam lithography. By using a single-mode low-confinement waveguide geometry the loss is further reduced to ~0.12 dB/cm. Secondly, we present improvement in within-device phase error in wavelength selective devices, a critical parameter which is a direct measure of line-width uniformity improvement due to the 193nm immersion system. In addition to these superior device performances, the platform opens scenarios for designing new device concepts using sub-wavelength features. By taking advantage of this, we demonstrate a cost-effective robust single-etch sub-wavelength structure based fiber-chip coupler with a coupling efficiency of 40 % and high-quality (1.1×105) factor wavelength filters. These demonstrations on the 193nm immersion lithography show superior performance both in terms of dimensional uniformity and device functionality compared to 248nm- or standard 193nmbased patterning in high-volume manufacture platform. Furthermore, using the wafer and patterning technology similar to advanced CMOS technology brings silicon photonics closer toward an integrated optical interconnect.
System performance scaling imposes an increase of package-to-package aggregate bandwidths to interface chips in high performance computing. This scaling is expected to encounter several I/O bottlenecks (pin count, speed, power consumption) when implemented in the electrical domain. Several optical interface technologies are being proposed among which silicon photonics, considered as a promising candidate. In this paper we will review the recent progress made in this technology that may enable multi-channel WDM links for package-to-package interconnects: 1.0V drivers with microring modulators and compact manufacturable microring filters with efficient thermal tuning.
In this paper we discuss silicon-based photonic integrated circuit technology for applications beyond the
telecommunication wavelength range. Silicon-on-insulator and germanium-on-silicon passive waveguide circuits are
described, as well as the integration of III-V semiconductors, IV-VI colloidal nanoparticle films and GeSn alloys on
these circuits for increasing the functionality. The strong nonlinearity of silicon combined with the low nonlinear
absorption in the mid-infrared is exploited to generate picosecond pulse based supercontinuum sources and optical
parametric oscillators that can be used as spectroscopic sensor sources.
A Si photonics platform is described, co-integrating advanced passive components with Si modulators and Ge detectors.
This platform is developed on a 200mm CMOS toolset, compatible with a 130nm CMOS baseline. The paper describes
the process flow, and describes the performance of selected electro-optical devices to demonstrate the viability of the
flow.
A compact electro-optic modulator on silicon-on-insulator is presented. The structure consists of a III-V microdisk cavity heterogeneously integrated on a silicon-on-insulator wire waveguide. By modulating the loss of the active layer included in the cavity through carrier injection, the power of the transmitted light at the resonant wavelength is modulated. ~10 dB extinction ratio and 2.73 Gbps dynamic operation are demonstrated without using any special driving techniques. The results are consistent with the theoretical simulations.
Silicon is excellent material for realizing compact nanophotonic ICs operating at wavelengths in the telecom
range. Moreover, the desired circuits can be realized with the most advanced equipment available, used also for
the fabrication of high-end electronic circuits. Efficient light emission and amplification directly from silicon
remains a bottleneck however. Therefore, we developed an alternative approach, based on the heterogeneous
integration of III-V epitaxial material and silicon nanophotonic circuits. Following fabrication and planarization
of the latter, small unprocessed dies of InP-based epitaxial material are bonded on top. Next, the substrate of
these dies is removed down to an etch stop layer. Finally the desired active optoelectronic devices are processed
in the remaining III-V layers using waferscale processes. The critical alignment between the sources and the
underlying nanophotonic circuits is ensured through accurate lithography. In this paper we review some recent
devices fabricated through this integration process.
We have achieved continuous-wave electrically-injected lasing operation at room-temperature in InP-based microdisks
heterogeneously integrated on a SOI nanophotonic circuit. The microdisks were evanescently coupled with sub-micron
SOI wire waveguides, resulting in up to 10 μW waveguide-coupled unidirectional output power, with a measured slope
efficiency up to 20 μW/mA. A tunnel junction was used for efficient electrical injection with low optical absorption. The
measured laser performance agrees well with calculations based on a standard laser model. This model suggests that
considerable improvement in laser performance is possible.
We fabricated single-mode photonic wires, nanophotonic waveguides confining light by total internal reflection. The structures are defined in silicon-on-insulator using 248nm deep UV lithography, a widely adopted technology for CMOS applications. The crystalline silicon core has a thickness of 220nm and a width of up to 600nm. A 1um thick silica layer serves as the lower cladding. We measured the loss of straight waveguides using the Fabry-Perot interference spectrum of the cleaved samples. A 500nm wide waveguide has a loss as low as 2.4dB/cm at 1550nm wavelength. We measured 90 degree bends to have excess losses of about 1dB. Mirror bends perform comparably. We fabricated symmetrically coupled ring and "racetrack" resonators with small radius. Q-factors higher than 3000 are achieved, leading to low add-drop crosstalk, high finesse and low at-resonance insertion loss. By fitting the theoretical model to the experimental results, we extracted parameters such as the coupling ratio, cavity loss and group index. We analyzed the fabrication tolerances allowed for these resonators to be suitable as a building block for WDM filtering components. The allowed deviation on the waveguide widths and gaps for the coupling ratio to be within specification are within the possibilities of the fabrication method. However, a method to tightly control the optical cavity length is needed as the ring's group index is highly dependent on waveguide width.
Nanophotonic ICs promise to play a major role in the future of opto-electronic signal processing and telecommunications. But for these devices, which consist of large numbers of wavelength-scale photonic components, to be successful, reliable and cost-effective mass-fabrication technology is needed. Photonic components, and among them photonic crystals, require a high degree of accuracy, which translates to low fabrication tolerances. Today, similar demands are made for high-end CMOS components, made of Silicon, for which a large manufacturing base is installed.
We demonstrate the fabrication of nanophotonic components, like photonic crystal waveguides and photonic wires, using state-of-the-art CMOS processing tools. The foremost of these is deep UV lithography at 248nm and 193nm, combined with dry-etch processes. To maintain compatibility with standard CMOS processes, we use Silicon-on-Insulator (SOI) as our material system. SOI is transparent at telecom wavelengths and provides a good substrate for high-index contrast optical waveguides. Moreover, recent studies have shown that nanophotonic components in SOI are less sensitive to surface roughness than similar components made in III-V semiconductor.
Although deep UV lithography cannot attain the resolution of e-beam lithography, this can be compensated with thorough process characterization, and the technique offers more speed because of its parallel nature. We will illustrate this with experimental results, and will also discuss some of the issues that have arisen in the course of this project.
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