This paper discusses mesh refinement methods used to perform Finite Element Analysis (FEA) for vibration based MEMS Energy Harvester. The three types of meshing elements, 1) Linear Hexahedral, 2) Parabolic Hexahedral and 3) Parabolic Tetrahedral, were used in this study. The meshing methods are used to ensure accurate simulation result particularly in stress, and strain analysis obtained, since they are determined by the displacement of each node in the physical structure. The study of the accuracy of an mesh analysis is also known as mesh convergence study which element aspect ratios must be refined consistently. In this paper the dimensions of each elements were also varied in order to investigate the significant of this methods in achieving better ratios of simulation to theoretical results.
This paper presents design and analysis of a 10GHz inductance-capacitance (LC)-Voltage-Controlled Oscillators (VCO)
implemented with a very high quality (Q) factor on-chip Micro-Electro-Mechanical Systems (MEMS) inductor using
0.25μm silicon-on-sapphire (SOS) technology. A new symmetric topology of suspended MEMS inductor is proposed to
reduce the length of the conductor strip and achieve the lowest series resistance in the metal tracks. This MEMS inductor
has been suspended above the high resistivity SOS substrate to minimise the substrate loss and therefore, achieve a very
high Q-factor inductor. A maximum Q-factor of 191.99 at 11.7GHz and Q-factor of 189 at 10GHz has been achieved for
a 1.13nH symmetric MEMS inductor. The proposed inductor has been integrated with a VCO on the same substrate
using the Metal layers in SOS technology removing the need for additional bond wire. The 10GHz LC-VCO has
achieved a phase noise of -116.27dBc/Hz and -126.19dBc/Hz at 1MHz and 3MHz of offset frequency, respectively. It
consumes 4.725mW of power from 2.5V supply voltage while achieving a Figure of Merit (FOM) of -189.5dBc/Hz.
This paper presents design of a Film Bulk Acoustic Wave Resonators (FBARs) consisting of piezoelectric film,
aluminium nitride (AlN) with top and bottom electrodes of ruthenium (Ru). The lumped Butterworth-Van Dyke (BVD)
Circuit model is used to investigate the theoretical harmonic response and extraction equivalent circuit of the FBAR. A
three-dimensional (3D) Finite Element Method (FEM) is used to evaluate the electro-mechanical performance of the
FBAR. The one-dimension (1D) numerical and the 3D FEM simulation results are analysed and compared. The results
show that coupling coefficient (k2eff) up to 7.0% can be obtained with optimised thickness ratio of electrode/piezoelectric
layers. A Figure of Merit (FOM) that considers k2eff and quality (Q) factor is used for comparison. The area of FBAR is
900μm2 and the active filter area size of the FBAR filter is 5400μm2. The FBAR filter is designed for operation in Kuband
with centre frequency of 15.5 GHz and fractional bandwidth of 2.6%. The proposed FBAR filter has insertion loss
of -2.3dB which will improve the performance of Ku-band transceiver and improve communication range and data rates
in Ku-band communication links.
Prototyping a Micro Electro Mechanical System (MEMS) device is a very different process to that employed for a
standard Integrated Circuit (IC) or Printed Circuit Board (PCB). While the manufacturing methods for MEMS devices
largely derive from the IC industry MEMS present many unique manufacturability challenges. These challenges
typically relate to two distinct features, specifically; mechanics of the device and the packaging of the device. This paper
discusses some of the potential pitfalls in the manufacture of a MEMS prototype; more specifically the paper considers
issues leading to low yield rates in a MEMS prototype developed by the authors and then discusses possible
improvements to enable a better chance of success. This discussion first identifies some of the more significant MEMS
sensor design features that contributed to a low yield and then presents design improvements that could significantly
increase the yield. Following this is the identification of several issues involved in packaging the sensor, which had the
effect of reducing the yield further; in this case improvements in the packaging are suggested. Also discussed are some
general prototyping problems researchers may face that with careful planning may be avoided.
KEYWORDS: Sensors, Microelectromechanical systems, Unmanned aerial vehicles, Structural health monitoring, Magnetism, Chemical elements, Temperature metrology, Control systems, Sensing systems, Lanthanum
Research into operational aspects of mini (<5kg) unmanned aerial vehicles (UAV) and structural health monitoring
systems (SHM) is being conducted at the Defence Science and Technology Organisation and La Trobe University. A
fundamental area of interest is investigating the problems associated with robustness of the control and health monitoring
sensors for such systems.
While many technologies for UAV and SHM systems can be, and have been, adapted from those currently available in
large manned aircraft; cost, weight, and size constraints have prevented mini UAVs from including many of the robust
mechanisms common to larger aircraft. Moreover, the ubiquitous nature of the sensing requirements for SHM systems
has limited their uptake, due mainly to the same issues of cost, weight and size.
This paper details the design of a reconfigurable multivariable MEMS (Micro Electro Mechanical System) array to
address these issues. This array is composed of multiple instances of identical sensors, which can be dynamically
reconfigured to achieve the desired measurand(s) with tradeoffs against accuracy. The available measurands include such
items as; accelerations, rotational rates, magnetic fields (X, Y and Z directions), temperature and pressure. The paper
presents the design of a reconfigurable multivariable MEMS sensor array together with simulation results.
KEYWORDS: Control systems, Human-machine interfaces, Sensors, Data storage, Intelligence systems, Data analysis, Climate change, Personal digital assistants, Lanthanum
Peak and average energy usage in domestic and industrial environments is growing rapidly and absence of detailed
energy consumption metrics is making systematic reduction of energy usage very difficult. Smart energy management
system aims at providing a cost-effective solution for managing soaring energy consumption and its impact on green
house gas emissions and climate change.
The solution is based on seamless integration of existing wired and wireless communication technologies combined with
smart context-aware software which offers a complete solution for automation of energy measurement and device
control. The persuasive software presents users with easy-to-assimilate visual cues identifying problem areas and time
periods and encourages a behavioural change to conserve energy.
The system allows analysis of real-time/statistical consumption data with the ability to drill down into detailed analysis
of power consumption, CO2 emissions and cost. The system generates intelligent projections and suggests potential
methods (e.g. reducing standby, tuning heating/cooling temperature, etc.) of reducing energy consumption. The user
interface is accessible using web enabled devices such as PDAs, PCs, etc. or using SMS, email, and instant messaging.
Successful real-world trial of the system has demonstrated the potential to save 20 to 30% energy consumption on an
average. Low cost of deployment and the ability to easily manage consumption from various web enabled devices offers
gives this system a high penetration and impact capability offering a sustainable solution to act on climate change today.
This paper presents the design and optimisation of three types of high Quality (Q) factor air suspended inductors
(symmetric (a), symmetric (b) and circular), using micro-electro-mechanical systems (MEMS) technology, for 10GHz to
20GHz frequency band. The geometrical parameters of inductor topology, such as outer diameter, the width of metal
traces, the thickness of the metal and the air gap, are used as design variables and their effects on the Q-factor and
inductance are thoroughly analysed. The inductor has been designed on high resistivity Silicon-on-Sapphire (SOS)
substrate in order to reduce the substrate loss and improve the Q factor. Results indicate that the proposed inductor
topology (symmetric (a)) has highest Q-factor with peak Q-factor of 192 at 12GHz for a 1.13nH inductance.
This paper presents the design and implementation of a fully on-chip wideband low noise amplifier (LNA) using 0.25-
micron Silicon-on-Sapphire (SOS) technology for the next-generation Square Kilometre Array (SKA) radio telescope
application. Ultra low noise and wideband operation are the principle design challenges in LNA for SKA application.
The proposed LNA design employs cascaded inductive degeneration architecture and achieves broadband matching by
using on-chip high quality factor (Q) SOS inductors inter-stage/intermediate LC matching circuit. Use of high Q
inductors results in low noise input matching circuit that enables the LNA to achieve the required minimum noise figure
(NF). The proposed LNA is a complete on-chip solution that achieves a NF from 0.57dB to 0.68dB over 1.1GHZ-band
with a minimum gain of 15.3dB. This design consumes only 40.78mW of power from a 2.5-V power supply.
This paper presents the design and implementation of an optimised MEMS-based reconfigurable VCO for a multi-standard
mobile terminal for GSM900, DCS1800 and WCDMA standards. In this VCO design, the passive components,
including inductors, capacitors and switches are replaced by MEMS components, to improve the system performance
and reduce the system power consumption. Moreover, a phase noise optimisation algorithm is also proposed to optimise
the VCO design for optimum system phase noise and minimum power consumption. Results show that a 50% reduction
of power consumption is achieved when the MEMS components are used instead of the passive components. A 31%
further reduction of power consumption is also achieved when the tail-current optimisation algorithm is applied. This
characteristic makes the VCO a better candidate for wireless communication applications where power consumption is
the major factor.
This paper presents an optimised low-power low-phase-noise Voltage Controlled Oscillator (VCO) for Bluetooth
wireless applications. The system level design issues and tradeoffs related to Direct Conversion Receiver (DCR) and
Low Intermediate Frequency (IF) architecture for Bluetooth are discussed. Subsequently, for a low IF architecture, the
critical VCO performance parameters are derived from system specifications. The VCO presented in the paper is
optimised by implementing a novel biasing circuit that employs two current mirrors, one at the top and the other one at
the bottom of the cross-coupled complementary VCO, to give the exact replica of the current in both the arms of current
mirror circuit. This approach, therefore, significantly reduces the system power consumption as well as improves the
system performance. Results show that, the VCO consumes only 281μW of power at 2V supply. Its phase noise
performance are -115dBc/Hz, -130dBc/Hz and -141dBc/Hz at the offset frequency of 1MHz, 3MHz and 5MHz
respectively. Results indicate that 31% reduction in power consumption is achieved as compared to the traditional VCO
design. These characteristics make the designed VCO a better candidate for Bluetooth wireless application where power
consumption is the major issue.
Ultra Wideband (UWB) communications is one of the possible solutions for future wireless personal area network (WPAN) applications. The Federal Communications Commission (FCC), in the USA, allocated 7.5 GHz of unlicensed frequency bandwidth from 3.1 GHz to 10.6 GHz for UWB communication. It is an available spectrum which can be utilised for data communication using different technologies complying with FCC regulations. This paper presents a brief overview of the world wide regulations and Institute of Electrical and Electronic Engineers (IEEE) standardisation updates for UWB. It also focuses on the wireless sensor network application and the use of UWB communications in biomedical sensor networks. The paper aims at the design and implementation of an optimised pulsed matched filter (OPMF) used in the digital backend of a UWB radio. The optimisations are performed at the architectural and circuit level in order to reduce hardware complexity and reduced power. The OPMF is successfully implemented using the application specific integrated circuit (ASIC) design methodology and the results are compared with those obtained in previous implementation. The OPMF implementation presented in this paper yields improved characteristics such as reduction in area, almost 25% power reduction and better timing.
Over the last few years, piezoelectric elements have gained popularity as a convenient and relatively inexpensive interface between the electrical and mechanical domains of power harvesting and vibration damping systems. Power harvesting is commonly performed by placing a bridge rectifier across the piezoelectric element and feeding the output into a capacitor and matched load, in much the same manner as used in a standard power supply circuit. However, the overall efficiency of the electrical power harvesting system using this approach can be quite low. Therefore, there is a continued search for circuit architectures and techniques to enhance the efficiency and performance of such systems. It is shown that using piezoelectric devices for electrical power harvesting is closely related to vibration damping using the same devices. This paper proposes that focusing on the reflected mechanical power could produce more efficient systems than focusing on electrical power transfer alone. In exploring this proposition an attempt was made to identify important parameters in the design of such systems. This exploration has demonstrated the importance of maximizing the voltage across the piezoelectric element as the primary means of maximizing the reflected mechanical power. Complexity and cost are often issues when operating piezoelectric devices at high voltages, which led to the development of a relatively simple charge polarity reversal mechanism. Such a mechanism has been demonstrated to improve the efficiency of energy harvesting and/or vibration damping. Simulation of this concept shows a substantial improvement over the bridge rectifier concept. Whilst the magnitude of improvement is dependent on how high the voltage across the piezoelectric element can be raised, the scenario shown in detail gives an improvement of approximately two orders of magnitude.
Reduction of power dissipations in CMOS circuits needs to be addressed for portable battery devices. Selection of appropriate transistor library to minimise leakage current, implementation of low power design architectures, power management implementation, and the choice of chip packaging, all have impact on power dissipation and are important considerations in design and implementation of integrated circuits for low power applications. Energy-efficient architecture is highly desirable for battery operated systems, which operates in a wide variation of operating scenarios. Energy-efficient design aims to reconfigure its own architectures to scale down energy consumption depending upon the throughput and quality requirement. An energy efficient system should be able to decide its minimum power requirements by dynamically scaling its own operating frequency, supply voltage or the threshold voltage according to a variety of operating scenarios. The increasing product demand for application specific integrated circuit or processor for independent portable devices has influenced designers to implement dedicated processors with ultra low power requirements. One of these dedicated processors is a Fast Fourier Transform (FFT) processor, which is widely used in signal processing for numerous applications such as, wireless telecommunication and biomedical applications where the demand for extended battery life is extremely high. This paper presents the design and performance analysis of a low power shared memory FFT processor incorporating dynamic voltage scaling. Dynamic voltage scaling enables power supply scaling into various supply voltage levels. The concept behind the proposed solution is that if the speed of the main logic core can be adjusted according to input load or amount of processor's computation "just enough" to meet the requirement. The design was implemented using 0.12 μm ST-Microelectronic 6-metal layer CMOS dual- process technology in Cadence Analogue Environment.
This paper presents the design and implementation of an intelligent data processing system for a wireless sensor node for healthcare application. The data processing system comprises of front-end sensors and a data acquisition (DAQ) system for signal processing. A smart property for the system has been developed so that it automatically selects the optimum method to 'condition' the biosignals, depending on the input channel requirements for better system accuracy. Moreover, it correspondingly selects an optimal sampling speed for each input channel to reduce the system power consumption, data storage and cost. Results show that a 47% reduction in power consumption is achieved and the aliasing error is reduced by 31% when the smart data processing architecture is used instead of traditional fix-rate data processing system.
This paper presents a detailed design and analysis of fringing and metal thickness effects in a Micro Electro Mechanical System (MEMS) parallel plate capacitor. MEMS capacitor is one of the widely deployed components into various applications such are pressure sensor, accelerometers, Voltage Controlled Oscillator's (VCO's) and other tuning circuits. The advantages of MEMS capacitor are miniaturisation, integration with optics, low power consumption and high quality factor for RF circuits. Parallel plate capacitor models found in literature are discussed and the best suitable model for MEMS capacitors is presented. From the equations presented it is found that fringing filed and metal thickness have logarithmic effects on capacitance and depend on width of parallel plates, distance between them and thickness of metal plates. From this analysis a precise model of a MEMS parallel plate capacitor is developed which incorporates the effects of fringing fields and metal thickness. A parallel plate MEMS capacitor has been implemented using Coventor design suite. Finite Element Method (FEM) analysis in Coventorware design suite has been performed to verify the accuracy of the proposed model for suitable range of dimensions for MEMS capacitor Simulations and analysis show that the error between the designed and the simulated values of MEMS capacitor is significantly reduced. Application of the modified model for computing capacitance of a combed device shows that the designed values greatly differ from simulated results noticeably from 1.0339pF to 1.3171pF in case of fringed devices.
KEYWORDS: Data acquisition, Control systems, Signal detection, Relays, Electronic filtering, Signal generators, Digital signal processing, Clocks, Error analysis, Application specific integrated circuits
This paper presents the application specific integrated circuit (ASIC) implementation of an intelligent controller for a reconfigurable data acquisition (DAQ) system. The DAQ system is employed in a digital relay for power system protection application. The controller is the intelligence behind the reconfigurable architecture. It continuously monitors the voltages and currents to detect the appearance of an abnormal condition on the power transmission network. Then it will send signals to adjust DAQ system sampling speed and filter cut-off frequency for properly detecting the fault location and properly analysing the fault. A novel approach to determine the line impedance angle has been proposed. This approach eliminates the square-root and arc-tan operations to reduce the cost of the semi-custom ASIC implementation of the intelligent controller. Analysis revealed that the intelligent controller achieved a maximum operating frequency of 100MHz, with 10ns critical path delay. The controller core utilises an area of 1.9mm2.
This paper presents a fully differential ultra low power successive approximation (SA) Analog-to-digital converter (ADC) for biomedical application. In order to reduce the system power consumption, the building block components of the SA ADC architecture has been optimised. In addition, the ADC the input voltage swing is scaled down to in order to reduce the slope gain error and the nonlinearity errors. The SA ADC has been implemented in Cadence Analog Design Environment using 0.18-micron CMOS technology. The designed SA ADC operates at a sampling rate of 200S/s at 3V power supply and consumes only 12µW of power at this frequency. The ADC standby power consumption is less than 1µW. The designed 16-bit ADC occupies an area of 0.1 mm2 and is the smallest in size among its 16-bit counter parts reported in the literature. The proposed 16-bit ADC achieves the differential-non-linearity (DNL) and integral-non-linearity errors (INL) of ± 0.5 LSB and ± 0.3 LSB respectively.
The two main sources of power dissipation in CMOS circuits are dynamic and static power dissipation. Static power dissipation is due to leakage current when the transistor is normally off. The improvement in technology scaling has introduced very large subthreshold leakage current, therefore careful design techniques are very important in order to reduce subthreshold leakage current for low power design. Leakage current occurs in both active and standby modes. It is recommended to switch off the leakage current when the circuit is in standby mode, however it is not always possible to shut off the leakage current completely during this mode. Unlike gate leakage, subthreshold leakage cannot be solved by MOS structures nor by introducing new material. One of the feasible solutions is by combinational use of Low-Vt transistors for its high-speed capability and High-Vt transistors for very small leakage current. Multi-Threshold CMOS (MTCMOS) and Variable-Threshold CMOS (VTCMOS) are biasing techniques that uses combinations of different threshold voltage and are suitable for SRAM design. Ideally the larger the threshold level the lower the leakage current, however, one must decide the optimum value of threshold level between the power switch (High-Vt devices) and (Low-Vt devices), as recovery delay tends to increase in higher threshold level. The full paper will discuss the design and performance of SRAM implemented using MTCMOS and VTCMOS biasing techniques. An improved sensing amplifier in the memory cell was incorporated to enhance the circuit performance.
Ultra-wideband (UWB) technology dates back to early 1980s and was originally employed in radar applications. Unlike any narrowband or broadband communication systems, an UWB system does not employ any radio frequency (RF) carrier for data transmission. Instead it uses very short period electrical pulses in the order of hundreds of pico-seconds to few nano-seconds, which justifies the availability of an ultra-high bandwidth. From a hardware implementation viewpoint, UWB system design presents many challenges such as synchronisation, power limitation and receiver design. However, the design of an UWB transceiver is less complex given the fact that the RF carrier is eliminated. In an UWB transceiver, most of the processing is performed in the digital baseband while the analog front end is
responsible for amplification, filtering and quantisation. A bank of matched filters constitutes the major portion of digital baseband section in an UWB transceiver. This paper presents the design, optimisation and field programmable gate array (FPGA) implementation of the matched filter bank as an attempt to minimise the overall circuit complexity, achieve higher data rates and low power consumption in UWB radios.
There has been significant growth in the wireless market where new applications are accompanied with strict design goals such as low cost, low power dissipation and small form factor. Large capacity and range for new applications are the driving force for development of new standard such as third generation mobile system (3G). Recent research results show that the development that was not possible with current IC technology is made possible with MicroElectroMechanical Systems (MEMS) technology. Significant amount of research is taking place to replace the off-chip components with on-chip components to design a high performance receiver front end. The passive components such as switches, capacitors and inductors are integral part of RF front end. High quality (Q) inductors are used to design RF front-end components such as voltage-controlled oscillator (VCO) and low noise amplifier (LNA). However, they are the bottleneck in achieving the on-chip optimum components, because of Q factor dependence on parasitic effects, limiting the performance. In recent research publications different on-chip inductor structures such as coil, polygon, rectangular and stacked configurations have been suggested and used to implement high value of inductance. In this paper design and implementation issues of MEMS inductor are presented. The paper is divided in two sections, the first section presents the role of MEMS based passive components and second section presents design issues, implementation and analysis of different MEMS based inductors.
The new MEMS technology has made a major impact on design of RF components. The results that were not possible with current IC technology are made possible with MEMS technology. Researchers are working to replace the off-chip components with on-chip components so as to achieve a single chip receiver. The high Q inductors and capacitors required for designing RF components are the bottleneck in achieving the single chip receiver. The main advantage of direct conversion architecture is fewer components are required for implementations, but there are certain design issues that must be taken care for these implementations to be successfully achieved. In this paper, MEMS components used within RF systems is analysed. The VCO is the most difficult block of RF front-end design having large impact on system performance; so stringent requirements are imposed on VCO phase noise performance. A typical range of MEMS component values are used to design and implementation the VCO.
This paper presents the performance analysis of different high-accuracy sample-and-hold circuit (SHC) techniques using CMOS technology. The paper begins with a detailed analysis of the major factors that limit the accuracy of a fundamental SHC. Then different techniques to implement high-accuracy SHCs are described. SHC employing transmission gate and SHC using feedback loop with compensation capacitor, as well as the fundamental SHC, were all implemented and tested and performance results demonstrate the superiority of each SHC schemes. For comparison reasons, the three SHCs were operated at a speed of 330 MHz. Results indicate that an increase of accuracy of 95% is achieved and the maximum sampling speed is increased by 15% when the SHC using feedback loop is used instead of the fundamental SHC. These characteristics make this device better candidate for many applications where speed and accuracy are the major factors.
KEYWORDS: Quantum efficiency, Digital signal processing, Clocks, Receivers, Quantization, Control systems, Signal attenuation, Safety, Electrical engineering, Standards development
A control unit has been proposed, which is used to reconfigure a pipeline ADC for a mobile terminal receiver that can drastically reduce the power dissipation dependent on adjacent channel interference. The proposed design automatically scales the word length by monitoring the quantization noise along the in-band and out-of-bands powers in the UTRA-TDD spectrum. The new ADC performance was evaluated in a simulation UTRA-TDD environment because of the large near far problem caused by adjacent channel interference from adjacent mobiles and base stations. Results show that by using the control unit to reconfigure the ADC, up to 88% power dissipation could be saved, when compared to a fixed 16 bits ADC without the use of the control unit. This will prolong talk and standby time in a moble terminal.
KEYWORDS: Digital signal processing, Filtering (signal processing), Electronic filtering, Digital filtering, Receivers, Signal processing, Optical filters, Safety, Statistical analysis, Linear filtering
A reconfigurable digital filter for a mobile terminal receiver has been analyzed in a simulated dynamic UTRA-TDD environment. By monitoring in-band and out-of-band power ratios, the filter architecture automatically scales its length to meet the signal to noise ratio of the system, This results in optimal battery power efficiency. Analysis reveals a 60 percent power saving for the receiver filter is available for the UTRA-TDD environment. This is compared to a static length filter that meets the 3GPP specifications. The savings in power will extend talk time and stand by time of the mobile terminal.
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