Sub-resolution assist feature (SRAF) insertion techniques have been effectively used for a long time now to increase process latitude in the lithography patterning process. Rule-based SRAF and model-based SRAF are complementary solutions, and each has its own benefits, depending on the objectives of applications and the criticality of the impact on manufacturing yield, efficiency, and productivity. Rule-based SRAF provides superior geometric output consistency and faster runtime performance, but the associated recipe development time can be of concern. Model-based SRAF provides better coverage for more complicated pattern structures in terms of shapes and sizes, with considerably less time required for recipe development, although consistency and performance may be impacted. In this paper, we introduce a new model-assisted template extraction (MATE) SRAF solution, which employs decision tree learning in a model-based solution to provide the benefits of both rule-based and model-based SRAF insertion approaches. The MATE solution is designed to automate the creation of rules/templates for SRAF insertion, and is based on the SRAF placement predicted by model-based solutions. The MATE SRAF recipe provides optimum lithographic quality in relation to various manufacturing aspects in a very short time, compared to traditional methods of rule optimization. Experiments were done using memory device pattern layouts to compare the MATE solution to existing model-based SRAF and pixelated SRAF approaches, based on lithographic process window quality, runtime performance, and geometric output consistency.
Traditionally, optical proximity correction (OPC) on cell array patterns in memory layout uses simple bias rules to correct hierarchically-placed features, but requires intensive, rigorous lithographic simulations to maximize the wafer process latitude. This process requires time-consuming procedures to be performed on the full chip (excluding the cell arrays) to handle unique cell features and layout placements before (and even sometimes after) OPC. The time required limits productivity for both mask tapeouts and the wafer process development. In this paper, a new cell array OPC flow is introduced that reduces turnaround-time for mask tapeouts from days to hours, while maintaining acceptable OPC quality and the perfect geometric consistency on the OPC output that is critical for memory manufacturing. The flow comprises an effective sub-resolution assist features (SRAFs) insertion and OPC for both the cell array and the peripheral pattern areas. Both simulation and experimental results from actual wafer verification are discussed.
Photolithography for the formerly "non-critical" implant blocking layers is becoming more challenging as edge
placement control budgets for junction definition shrink with each node. In addition to the traditional proximity
effects associated with the implant layer mask, the underlying active and gate layers can interact through a variety of
mechanisms to influence the edge placement of the developed implant layer. These mechanisms include bulk
reflectivity differences, resist thickness thin film interference effects, reflective notching from pattern sidewalls,
reflections from curved surfaces, focus differences, and more. While the use of organic developable bottom
antireflection coating (dBARC) can be effective in minimizing these influences, it does represent an added
complexity and cost, and processes are still relatively immature. Without such a dBARC, the CD variation due to
underlying layers can easily exceed 50 nm, or more than 25% of the target dimension. We propose here a
framework for modeling and correcting for these underlayer effects. The approach is based upon calibration of an
optical model representing only implant mask proximity effects and two additional optical models which represent
the effects of the underlayer topography. Such an approach can be effective in delivering much improved CD
control for complex layouts, and represents only a small impact to full-chip correction runtime.
As the industry progresses toward smaller patterning nodes with tighter CD error budgets and narrower process
windows, the ability to control pattern quality becomes a critical, yield-limiting factor. In addition, as the feature size of
design layouts continues to decrease at 32nm and below, optical proximity correction (OPC) technology becomes more
complex and more difficult. From a lithographic point of view, it is the most important that the patterns are printed as
designed. However, unfavorable localized CD variation can be induced by the lithography process, which will cause
catastrophic patterning failures (i.e. ripple effects, and severe necking or bridging phenomenon) through process
variation. It is becoming even more severe with strong off-axis illumination conditions and other resolution enhancement
techniques (RETs). Traditionally, it can be reduced by optimizing the rule based edge fragmentation in the OPC setup,
but this fragmentation optimization is very dependent upon the engineer's skill. Most fragmentation is based on a set of
simple rules, but those rules may not always be robust in every possible design shape.
In this paper, a model based approach for solving these imaging distortions has been tested as opposed to a previous
rule based one. The model based approach is automatic correction techniques for reducing complexity of the OPC recipe.
This comes in the form of automatically adjusting fragments lengths along with feedback values at every OPC iterations
for a better convergence. The stability and coverage for this model based approach has been tested throughout various
layout cases.
A Pixel-based sub-resolution assist feature (SRAF) insertion technique has been considered as one of the promising
solutions by maximizing the common process window. However, process window improvement of the pixel-based
SRAF technique is limited by the simplification of SRAFs for mask manufacturability. Mask simplification and mask
rule check (MRC) constraints parameters for pixel-based SRAF technique are the critical factors for mask production
without a big loss of its benefit. In this study, correlation of MRC control was analyzed in terms of the robustness to
process variation for a contact layer of 32nm device node. An optimum condition of MRC constraints was selected by
balancing the process window and mask manufacturability. In addition, a novel and practical methodology for 32nm
device node development was proposed to keep the mask complexity low and to take full advantage of process window
improvement using pixel-base SRAF insertion.
MEEF (Mask Error Enhancement Factor) has become a critical factor in CD uniformity control since optical lithography process moved to sub-resolution era. A lot of studies have been done by quantifying the impact of the mask CD (Critical Dimension) errors on the wafer CD errors1-2. However, the benefits from those studies were restricted only to small pattern areas of the full-chip data due to long simulation time. As fast turn around time can be achieved for the complicated verifications on very large data by linearly scalable distributed processing technology, model-based lithography verification becomes feasible for various types of applications such as post mask synthesis data sign off for mask tape out in production and lithography process development with full-chip data3,4,5. In this study, we introduced two useful methodologies for the full-chip level verification of mask error impact on wafer lithography patterning process. One methodology is to check MEEF distribution in addition to CD distribution through process window, which can be used for RET/OPC optimization at R&D stage. The other is to check mask error sensitivity on potential pinch and bridge hotspots through lithography process variation, where the outputs can be passed on to Mask CD metrology to add CD measurements on those hotspot locations. Two different OPC data were compared using the two methodologies in this study.
Gate CD (Critical Dimension) control is an important factor in determining semiconductor manufacturing yield. Therefore, its verification prior to mask tape-out is essential to save development time and cost. Not only is fatal-error detection required to ensure high yield, tight CD control in the gate region is equally critical in sub-micron IC manufacturing.
As fast turn around time is achieved for very large data through scalable distributed processing, model-based lithography verification has been utilized for checking the post mask synthesis data quality before mask tape out and RET/OPC process development.
In this paper, we introduce a comprehensive methodology to study and qualify Poly mask layer using a model based lithography verification tool. This flow will include CD checks on both gate-width and gate- length dimensions. Gate CD distribution plots on the poly layer will be done across a complete range of target CDs in order to investigate wafer CD uniformity errors on full-chip level under various process conditions. In addition, the traditional edge-placement detection will be discussed and compared to absolute CD verification process.
Contact and via layers are becoming more critical than before from lithography point of view due to the fact that the contact and via sizes for advanced devices are falling into deep sub-wavelength ranges. In this study, we will demonstrate several different methodologies for contact and via CD variation check and contact/metal overlay checks on the post-opc data using a model based verification software platform. Our study reveals that the full chip verification for the contact and via layers is necessary
achievable to guarantee the mask data quality and to prevent catastrophic pattern errors resulting from improper OPC corrections. Good scalability of the software methodology and platform makes it possible to do the full chip verification with reasonable turn around
time.
Model based full-chip lithography verification has been proven as a mask sign off solution to prevent patterning failures caused by design/OPC (Optical Proximity Correction) before mask data tape out. Furthermore, as the fast turn around time is achieved through scalable distributed processing for very large data after mask synthesis conversion such as assist feature and OPC, model-based full-chip verification can take advantages of RET (Resolution Enhancement Technique)/OPC recipe development. In previous studies, we introduced the full-chip verification methodologies for mask sign off flow in production and for RET/OPC optimization flow in process development stage for sub-wavelength lithography processes in general.
In this paper, we demonstrated the layer-specific verifications for critical layers for 65nm lithography process development. For poly layer, we performed various types of checks such as fatal pinch/bridge hotspots, CD variations, line-end/space-end errors, assist feature printability, MMEF (Mask Error Enhancement Factor) and geometrical (Mask Rule/structural) checks considering the mask manufacturing constraints. We compared hyper NA (Numerical Aperture)illumination using immersion lithography with the double expose alternating PSM (Phase Shift Mask) lithography. For metal layer, various full-process window coverage verification methodologies were discussed.
Resolution enhancement techniques and OPC(Optical Proximity Correction) have been developed with empirical data points from general test patterns and some actual patterns extracted from full-chip design. Lithography simulation tools have been used for intensive process simulation to optimize RET solutions using sample patterns to cover whole full-chip patterns. However, as design complexity increases and mask manufacturing rules restrict process proximity correction coverage, post-RET/OPC data can generate fatal patterning failures at locations where the process window is marginal. Therefore, it is necessary to identify those patterns from full-chip layout to choose proper RET/OPC solutions. Previously, it was proven that model based full-chip verification tool is useful to capture potential fatal patterning failures before mask tape-out sign-off for sub-wavelength lithography processes. [1] In this paper, we extended the full-chip verification methodology to quantitative RET/OPC development using database error analysis. First, using GDS data containing design intent only and a single 90nm lithography process calibrated model, we performed full-chip verification for linearly scaled designs through 130nm, 90nm and 65nm node to take OPC directions. Second, a standard OPC recipe was applied for each design node followed by verification. And then, potential pattern failures at 65nm node were analyzed through lithography process window. Finally, RET/OPC solution was discussed for 65nm design.
OPC (Optical Proximity Correction) improves the feature CD (critical dimension) uniformity and pattern fidelity in general. However, since model calibration only takes CD measurements at optimum exposure dose and best focus condition, the correction result may not be desirable at non-optimum conditions due to significant sub-resolution process distortion. Certain specific patterns are prone to bridging or pinching (we refer this type of location as hotspot in this paper) when process drifts a little from optimum condition. Simulation based full-chip verification became the method of choice for capturing hotspots on post-OPC layouts prior to mask tape-out to save development time and cost. In this paper, a complete simulation and analysis flow using SiVL was experimented to capture hotspots for a 100nm node process. Calibrated process model and multiple optical models with different focus/threshold conditions were applied for simulation. The method and effectiveness of filtering and analyzing fatal errors from output error database was discussed. The analysis results were then correlated to actual wafer printing. A good match between prediction and experiment was found.
We investigated KrF attenuated PSM defect printability for 120nm node actual DRAM lithography process. A programmed defect mask was fabricated for the experiment, which contains three different background pattern layers of isolation, bit lines, and bit line contact holes of the 120nm DRAM device. Various types and sizes of MoSi defects such as extensions, intrusions, dots, and holes were programmed on those background patterns. We used a high NA DUV scanner and high contrast resist for wafer printing test. Based on the experimental results, we defined the non-printable defect sizes of MoSi defects and evaluated the detection capabilities of i-line inspection tools for those printable defects. In addition, we tested repair performance of current tools by comparing the process windows of defect patterns between pre-repair and post-repair.
Optical lithography is pushed more to extend to sub-wavelength region for very low k1 patterning processes; in which, alternating PSM is the solution for isolated patterns, without changing the wavelength of exposure tools' light source. With this prospect, the critical issues such as design layout complexity, light intensity imbalance between shifted and unshifted space area, and phase defect controllability have recently been studied in order to apply alternating PSM for device mass production. In this paper, we studied to find out the maximum non-printable phase defects for 130 nm and 100 nm lines by printing the wafer using a KrF DUV scanner. With the limitations of the mask making process for very small programmed defects, we made the masks with duty ratio around 1:3. After we verified the resist simulation for our test pattern by wafer printing results, printable defects for denser pattern were predicted. In addition to defect printability study, the mechanical repair tool for phase bump defects was tested using 248 nm AIMS, AFM, and CD SEM metrology as well as wafer printing. Electromagnetic Field 3 dimension simulation was also compared with commercialized 2D simulation tool for phase defect printability.
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