Mr. Jun-Cheng Nelson Lai Profile

Jun-Cheng Nelson Lai

Dept Manager at Powerchip Semiconductor Manufacturing Corp

SPIE Involvement:

Author

Proceedings Article | 26 May 2022 Presentation + Paper

A novel approach of virtual etch target (VET) for efficient litho-to-etch pattern fidelity correction

Shr-Jia Chen, Yi-Shiang Chang, Chia-Chi Lin, Jun-Cheng Lai

Proceedings Volume 12052, 120520I (2022) https://doi.org/10.1117/12.2612298

KEYWORDS: Etching, Optical proximity correction, Logic, Lithography, Data modeling, Semiconducting wafers, Optical lithography, Double patterning technology

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For 28 nm node semiconductor devices and beyond, more aggressive resolution enhancement techniques (RETs) such as sub-resolution assist features (SRAF), litho-etch-litho-etch (LELE), self-aligned double patterning (SADP), self-aligned quadruple patterning(SAQP), and source-mask optimization (SMO) are utilized for the low k1 factor lithography processes. The litho-to-etch pattern fidelity is extremely critical since a slight lithography pattern weakness (ex: photoresist (PR) thickness loss, profile roughness ...) may be worsened after etch process due to the pattern loading effect, which will then induce physical defects that affect the final electrical performance. Rigorous lithography simulation can provide a reference of pattern weaknesses to modify mask layouts; but it is incapable of full-field mask data preparation. The post-etch critical dimensions (CDs) with a high accuracy optical proximity correction (OPC) model has become an important component; but it requires massive wafer data of post-litho and post-etch CDs, and will increase the runtime of the OPC flow for OPC modelers. In our previous submission [1-2], we had brought forth an algorithm that utilizes multi-intensity levels from conventional aerial image simulations to assess the physical profile through lithography to etch steps, and proposed a novel litho-etch correction method without suffering the lithography process window of SADP process. In this paper, we have improved this methodology and introduced a new approach of virtual etch target (VET) with virtual etch target threshold to assess post-etch CDs for various applications of memory patterning (dense features by SADP or SAQP process) and logic patterning (random features of lines, trenches and holes) more efficiently. The results not only matched post-etch wafer data, but also agreed with post-etch process window. Furthermore, this methodology can be utilized in generic OPC and post-OPC verification procedures to improve final pattern fidelity for logic and memory products.

Proceedings Article | 26 May 2022 Poster + Presentation + Paper

Effective OPC model calibration using machine learning

Yi-Hao Huang, Shin-Shing Yeh, Yung-Ching Mai, Chia-Chi Lin, Jun-Cheng Lai

Proceedings Volume 12052, 120521C (2022) https://doi.org/10.1117/12.2611337

KEYWORDS: Data modeling, Calibration, Optical proximity correction, Machine learning, Statistical modeling, Process modeling, Lithography, Principal component analysis, Optics manufacturing, Semiconductors

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Proceedings Article | 20 March 2019 Paper

An OPC approach to improve logic gate features corner fidelity

Ping-Hung Lin, Tzu-Chi Chao, Shin-Shing Yeh, Yung-Ching Mai, Lawrence Lin, Nelson Lai

Proceedings Volume 10961, 109610S (2019) https://doi.org/10.1117/12.2515443

KEYWORDS: Optical proximity correction, Lithography

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Proceedings Article | 28 March 2017 Paper

A fast process development flow by applying design technology co-optimization

Yi-Chieh Chen, Shin-Shing Yeh, Tsong-Hua Ou, Hung-Yu Lin, Yung-Ching Mai, Lawrence Lin, Jun-Cheng Lai, Ya Chieh Lai, Wei Xu, Philippe Hurat

Proceedings Volume 10148, 1014815 (2017) https://doi.org/10.1117/12.2257973

KEYWORDS: Lithography, Optical proximity correction, Machine learning, Databases, Integrated circuit design, Manufacturing, Metals, Semiconductor manufacturing, Transistors, Raster graphics

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Proceedings Article | 27 March 2017 Presentation + Paper

A novel methodology for litho-to-etch pattern fidelity correction for SADP process

Shr-Jia Chen, Yu-Cheng Chang, Arthur Lin, Yi-Shiang Chang, Chia-Chi Lin, Jun-Cheng Lai

Proceedings Volume 10146, 101460N (2017) https://doi.org/10.1117/12.2258201

KEYWORDS: Lithography, Photoresist materials, Etching, Optical proximity correction, Resolution enhancement technologies, Photomasks, Semiconductors, Source mask optimization, Double patterning technology, Semiconducting wafers, Radon, Computer simulations

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Proceedings Article | 24 March 2017 Paper

Advanced application of pattern-aware OPC

James Chen, Shin-Shing Yeh, Alan Zhu, Bayram Yenikaya, Fan-Hsuan Hsu, Yung-Ching Mai, Lawrence Lin, Nelson Lai

Proceedings Volume 10147, 101471W (2017) https://doi.org/10.1117/12.2258331

KEYWORDS: Optical proximity correction, Resolution enhancement technologies, Model-based design, SRAF, Lithography, Process control, Computational lithography, Pattern recognition, Yield improvement, 193nm lithography, Optical lithography

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Proceedings Article | 3 April 2010 Paper

Full area pattern decomposition of self-aligned double patterning for 30nm node NAND FLASH process

Yi-Shiang Chang, Jason Sweis, Jun-Cheng Lai, Chia-Chi Lin, Jonathan Yu

Proceedings Volume 7637, 76371N (2010) https://doi.org/10.1117/12.845831

KEYWORDS: Photomasks, Double patterning technology, Metals, Electronic design automation, Lithography, Optical proximity correction, Computer simulations, Electron beam lithography, Etching, Manufacturing

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Proceedings Article | 4 March 2010 Paper

Impact of scanner signatures on optical proximity correction

Jacek Tyminski, Tomoyuki Matsuyama, Yen-Liang Lu, Jun-Cheng Lai, Kao-Tun Chen, Yung-Ching Mai, Irene Su, George Bailey

Proceedings Volume 7640, 76400V (2010) https://doi.org/10.1117/12.845061

KEYWORDS: Optical proximity correction, Scanners, Photomasks, Fiber optic illuminators, Cadmium, Integrated circuits, Metrology, Tolerancing, Integrated optics, Diffraction

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Proceedings Article | 4 March 2010 Paper

Examining reflectivity criterion for various ArF lithography

Meng-Feng Tsai, Chia-Chi Lin, Wei-Chun Chao, Chan-Tsun Wu, Jun-Cheng Lai

Proceedings Volume 7640, 76403H (2010) https://doi.org/10.1117/12.848324

KEYWORDS: Reflectivity, Reflection, Lithography, Resolution enhancement technologies, Optical proximity correction, Bottom antireflective coatings, Photoresist processing, Carbon, Lithographic illumination, Double patterning technology

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Proceedings Article | 4 March 2010 Paper

The impact of resist model on mask 3D simulation accuracy beyond 40nm node memory patterns

Kao-Tun Chen, Shin-Shing Yeh, Ya-Hsuan Hsieh, Jun-Cheng Lai, Stewart Robertson, John Biafore, Sanjay Kapasi, Arthur Lin

Proceedings Volume 7640, 76401S (2010) https://doi.org/10.1117/12.846010

KEYWORDS: 3D modeling, Photomasks, Data modeling, Calibration, Performance modeling, 3D image processing, Semiconducting wafers, Seaborgium, Instrument modeling, Optical simulations

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Proceedings Article | 24 March 2009 Paper

Fast analysis and diagnostics for improving overlay control: moving beyond the black box approach

Yi-An Liu, Wei-Ming Wu, Hsiao-Chiang Lin, Jun-Cheng (Nelson) Lai, Chin-Chou (Kevin) Huang, Hsing-Chien (Robert) Wu, Healthy Huang, David Tien

Proceedings Volume 7272, 72722Z (2009) https://doi.org/10.1117/12.812478

KEYWORDS: Overlay metrology, Semiconducting wafers, Scanners, Error analysis, Reticles, Control systems, Diagnostics, Process control, Metrology, Process engineering

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Proceedings Article | 23 March 2009 Paper

Alignment method of self-aligned double patterning process

Meng-Feng Tsai, Jun-Cheng Lai, Yi-Shiang Chang, Chia-Chi Lin

Proceedings Volume 7272, 72721Q (2009) https://doi.org/10.1117/12.813641

KEYWORDS: Optical alignment, Overlay metrology, Signal processing, Double patterning technology, Photomasks, Etching, Optical lithography, Semiconducting wafers, Manufacturing, Scanners

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Proceedings Article | 16 March 2009 Paper

Pattern decomposition and process integration of self-aligned double patterning for 30nm node NAND FLASH process and beyond

Yi-Shiang Chang, Meng-Feng Tsai, Chia-Chi Lin, Jun-Cheng Lai

Proceedings Volume 7274, 72743E (2009) https://doi.org/10.1117/12.814000

KEYWORDS: Photomasks, Double patterning technology, Etching, Lithography, Semiconducting wafers, Manufacturing, Electron beam lithography, Bridges, Optical alignment, Scanners

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Showing 5 of 13 publications

Conference Committee Involvement (3)

SPIE Lithography Asia - Korea

13 October 2010 | n/a, Republic of Korea

SPIE Lithography Asia - Taiwan

18 November 2009 | Taipei, Taiwan

SPIE Lithography Asia - Taiwan

4 November 2008 | Taipei, Taiwan

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