Silicon photonics platforms leveraging 300mm manufacturing fabrication plants is a growing sector. This trend will continue as the demand for energy efficient data centers, advanced quantum computing architectures and AR/VR drive demand forward. GlobalFoundries is at the forefront of advanced photonics platforms implementation and have recently announced it is collaborating with industry leaders to deliver innovative, unique, feature-rich solutions to solve some of the biggest challenges facing data centers today. In this paper we investigate the impact of process manufacturing techniques typically used in advanced logic and memory on photonics waveguides uniformity improvement and smoothing. Some focus will be placed on the patterning process itself investigating effects of plasma VUV cure, direct current superposition and area selective deposition on resist for downstream line edge roughness and line width roughness impact. We will also review impact of silicon nitride film uniformity and top roughness smoothing on final waveguide optical performance. While silicon photonics features are much larger than logic features, process requirements to achieve required optical performance are stringent and will require innovative solutions to continue driving down optical losses.
As the limits of EUV single exposure direct printing are being explored there is a need for etch processes that can transfer small features and reduce defectivity. The implementation of high numerical aperture (NA) EUV scanner tool will allow for printing of sub-10 nm features in a single exposure. However, it reduces the depth of focus, thus requires thinner photoresist coatings. In preparation for high NA (0.55) we explore the etch implications of thin EUV photoresists. Here we show two different strategies for bridge defect reduction during etch and break elimination with selective deposition during the etch process.
In this study we examine several innovations. In lithography, we introduce our latest progress on metal oxide resist (MOR) to extend defectivity window, improve photo-speed, and wafer uniformity control by leveraging new resist development techniques.
On the plasma etch front, we focus on plasma-resist interactions and the impact of the pattern transfer process. Gas chemistry and plasma characteristics can modulate resist rectification, leading to a widening of the defectivity window and smoothing of pattern roughness. Especially, when reducing line-space pattern defectivity, correlations between plasma characteristics and microbridge defect numbers point to a proper process regime for patterning in the sub 30nm pitch era.
EUV (extreme ultraviolet) lithography has been introduced in high volume manufacturing in 2019 and continuous improvements have allowed to push the lithographic performance to the limits of 0.33 NA single exposure. However, stochastic failures, pattern roughness and local critical dimension uniformity (LCDU) are still major challenges that need to be addressed to maintain node shrinkage and improve yield. Together with pitch downscaling, photoresist thickness is decreasing to prevent pattern collapse. A lower depth of focus is also expected with high NA EUV which might even thin further down the resist layer. Being able to transfer the patterns with good fidelity is therefore getting very challenging because the resist “etch budget” is becoming too small to prevent pattern break during plasma etch transfer. A co-optimization of lithography processes, underlayers coating and etch processes is essential to further support the EUV patterning extension.
In this report, recently developed hardware and process solutions to stretch the limits of EUV patterning will be presented. The latest performance for both chemically amplified resists (CAR) and metal oxide resists (MOR) will be introduced, with a focus on defect mitigation, dose reduction strategies and CD stability.
In this talk we present core technology solutions for EUV Patterning and co-optimization between EUV resist and underlayer coating, development and plasma etch transfer to achieve best in class patterning performance. We will introduce new hardware and process innovations to address EUV stochastic issues, and present strategies that can extend into High NA EUV patterning. A strong focus will be placed on dose reduction opportunities, thin resist enablement and resist pattern collapse mitigation technologies. CAR and MOR performance for leading edge design rules will be showcased. As the first High NA EUV scanner is scheduled to be operational in 2023 in the joint high NA lab in Veldhoven, Tokyo Electron will collaborate closely with imec, ASML and our materials partners to accelerate High NA learning and support EUV roadmap extension.
KEYWORDS: Line edge roughness, System on a chip, Extreme ultraviolet, Plasma, Etching, Lithography, Silicon, Double patterning technology, Line width roughness, Extreme ultraviolet lithography
Extreme ultraviolet lithography (EUVL) has been adopted into high volume production for advanced logic device manufacturing. Due to the continuous size scaling requirement for interconnect fabrication, EUVL with self-aligned double patterning (SADP) formation has attracted substantial research attention. The current challenge in EUV SADP is the pattern transfer process from lithography to mandrel formation. In this step, the target critical dimension (CD) of the feature needs to shrink by half from the lithography CD during the etch process. The increasing aspect ratio during this etch potentially deteriorates the pattern validity and the line edge roughness (LER). In addition to these challenges, EUVL has a fundamental bottleneck due to stochastic effects, which can lead to device degradation by defect formation and edge placement error (EPE). LER of the line and space pattern is one of the main contributors to EPE. Effective methods of LER reduction in both process and integration are needed in order to reduce pattern variation and boost device performance. In our study, we examine a technique to reduce LER on the EUV SADP line pattern. This technique involves the surface modification on the spin-on carbon (SOC) layer in the patterning stack and tone inversion process. We had found a trend between surface hydrophobicity of the SOC and the EUV SADP LER performance. The condition that increased the hydrophobicity of the SOC resulted in a lower LER performance after tone inversion. The tested conditions include direct current superposition (DCS) function with H2 plasma, fluorocarbon plasma, and the combination of DCS with H2 plasma and trimethylsilane dimethylamine deposition. On 20-nm pitch EUV SADP, this technique shows 26% of LER improvement from lithography to SADP formation. PSD analysis recorded about 6% and 30% of the LER improvement at the correlation length of >200 nm and 200 to 30 nm, respectively. A demonstration of this technique for a further scaling to 15-nm pitch also shows an LER reduction of 30% from lithography to SADP formation.
Extreme ultraviolet lithography (EUVL) has been adopted into high volume production for advanced logic device manufacturing. Due to the continuous size scaling requirement for interconnect fabrication, EUVL with self-aligned double patterning (SADP) formation has attracted substantial research attention [1]–[6]. Double patterning techniques in EUVL achieve pitch halving in the final feature by using the spacer defined approach and self-aligned block (SAB) mitigates the block placement error by leveraging etch selectivities and material filling capability. The current challenge in EUV SADP is the pattern transfer process from lithography to mandrel formation. In this step, the target critical dimension (CD) of the feature needs to shrink by half from the lithography CD during the etch process. The increasing aspect ratio during this etch potentially deteriorates the pattern validity and the line edge roughness (LER) [5]. In addition to these challenges, EUVL has a fundamental bottleneck due to stochastic effects which can lead to device degradation by defect formation and edge-placement-error (EPE) [7]–[10]. LER of the line and space pattern is one of the main contributors to EPE. Effective methods of LER reduction in both process and integration are needed in order to reduce pattern variation and boost device performance. In our research, we examine three approaches to reduce LER on the EUV SADP line pattern. This includes photoresist surface smoothing techniques, patterning layer material study, and tone inversion integration. The photoresist surface smoothing techniques involve a specific plasma process on the EUV chemical amplified resist (CAR) to achieve > 15% of improvement on LER from lithography to post etch performance. The patterning layer material study reveals an optimum patterning stack to minimize etch-induced line wiggling and etch selectivity requirements for LER performance. Finally, a first demonstration of EUV SADP tone inversion process integration is presented as a method to provide additional benefits to LER reduction. A detailed analysis of line performance from each processing step will be examined.
As EUV direct patterning begins to hit its resolution limit, the need for EUV self-aligned double patterning (SADP) has arisen in order to reach sub-30 nm pitch. Currently, EUV resists suffer from several shortcomings, both in terms of roughness and resist budget. These constraints means using it directly as a mandrel material, as previously done for immersion lithography SADP is nearly impossible. Consequently, standard EUV SADP flows involve the transfer of the resist through a lithography stack and into a hard mandrel material, such as silicon nitride or amorphous silicon.1 Achieving line edge roughness (LER) and line width roughness (LWR) targets for an EUV SADP hard mandrel is significantly more challenging than for EUV direct print since the etch process needs to target a post etch CD of about half that of the lithographic CD. This aggressive shrink requirement usually involves degradation in roughness driven by high aspect ratios. To circumvent these issues, we have developed a new bottom up organic mandrel growth process, whereby the EUV resist can be grown to a height compatible with a resist mandrel SADP flow, while the roughness is improved and the critical dimension is controlled. This bottom up mandrel growth process is performed in an etch chamber and can therefore be easily coupled with other process steps. The mandrel height and critical dimensions can be easily tuned from the incoming lithography by changing the deposition and trim step times of the process. We have shown that this bottom-up grown mandrel can withstand typical ALD spacer process deposition. After spacer open, the organic material can be easily removed through an in-situ ash process before opening the underlayer. This integration will allow for the removal of the organic planarizing layer in the lithography stack, reducing the stack complexity, while also eliminating one of the major contributors to wiggling in the typical hard mandrel patterning scheme. In this paper, the performance of this new integration scheme was benchmarked against a more standard SADP flow. The roughness performance post mandrel formation and post spacer deposition for this new scheme is significantly improved over our standard EUV SADP baseline using a standard EUV SADP flow.
As future patterning processes reach the limit of lithographic printability, continuous innovation in mandrel trim or shrink strategies are required to reach sub-20 nm line-space patterning. Growing concerns of lithography defectivity, mask selectivity, line edge roughness (LER), line width roughness (LWR), and critical dimension uniformity (CDU) present significant challenges towards this goal. The authors compare various alternative mandrel trim strategies to highlight potential solutions and drawbacks towards enabling successful printing of mandrels used in extreme ultraviolet (EUV) multi-patterning schemes. Through this comparison, the authors demonstrate the challenges of maintaining adequate pattern transferability while keeping aspect ratio-driven line roughness and material selectivity under control. By process partitioning, the limitations of traditional lithography and etch trimming strategies are highlighted, suggesting the need for new methods of CD reduction after the pattern has been transferred. These new trimming methods offer flexibility in CD control without negatively impacting the mandrel profile and demonstrates better tunability across different material sets, allowing for evaluation of different mask and mandrel material combinations for downstream process optimization.
Patterning at 10 nm and sub-10 nm technology nodes is one of the key challenges for the semiconductor industry. Several patterning techniques are under investigation to enable the aggressive pitch requirements demanded by the logic technologies. EUV based patterning is being considered as a serious candidate for the sub-10nm nodes. As has been widely published, a new technology like EUV has its share of challenges. One of the main concerns with EUV resists is that it tends to have a lower etch selectivity and worse LER/LWR than traditional 193nm resists. Consequently the characteristics of the dry etching process play an increasingly important role in defining the outcome of the patterning process.
In this paper, we will demonstrate the role of the dual-frequency Capacitively Coupled Plasma (CCP) in the EUV patterning process with regards to improving LER/LWR, resist selectivity and CD tunability for holes and line patterns. One of the key knobs utilized here to improve LER and LWR, involves superimposing a negative DC voltage in RF plasma at one of the electrodes. The emission of ballistic electrons, in concert with the plasma chemistry, has shown to improve LER and LWR. Results from this study along with traditional plasma curing methods will be presented. In addition to this challenge, it is important to understand the parameters needed to influence CD tunability and improve resist selectivity. Data will be presented from a systematic study that shows the role of various plasma etch parameters that influence the key patterning metrics of CD, resist selectivity and LER/LWR. This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities.
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