This paper proposes new scanner fleet management utilizing programmed hotspot patterns.
We have developed a methodology to control and adjust critical parameters of scanner, such as effective illumination
shape and numerical aperture (NA), to obtain the same lithography performance. The purpose is to improve hotspot
patterns and depth of focus (DOF) of each scanner. The method is carried out with a test mask having programmed
hotspot patterns that are likely to become fatal errors for circuit reliability in wafer processing. Actual circuit patterns
whose patterning fidelity is sensitive to the critical parameters are selected as the programmed hotspots. The mask also
has various lithography process monitor marks, such as flare monitor pattern, MEF evaluation pattern and aberration
monitor pattern, for OPE control and simulation. Using the same test mask for every scanner, we can reveal the variation
of lithography performance within a "scanner fleet".
The hotspot patterns on the mask and the patterns printed onto wafers are inspected by Die-to-Database (D2DB) EB
inspection and a wafer D2DB EB inspection, respectively. Using those D2DB inspection systems, we can evaluate
quantitatively the change of pattern shape from drawing data to wafer. The OPE adjustment and OPC feedback are
corrected by using the simulation data acquired for the D2DB inspection. The quality of the evaluation provides accurate
scanner fleet control, resulting in high productivity and cost effectiveness at wafer fabrication.
Hotspot management in low k1 lithography is essential for the achievement of high yield in the manufacture of devices. We have developed a mask quality assurance system with hotspot management based on lithography simulation with SEM image edge extraction of actual mask patterns. However, there are issues concerning this hotspot management from the viewpoint of hotspot sampling and turnaround time.
To solve these problems, we modify the mask quality assurance system by introducing dynamic adaptive sampling in which hotspots are sampled depending on actual mask fabrication quality. As a result, producer's and consumer's risks are efficiently reduced, and TAT for mask inspection is also reduced.
We have designed the lithography process for 32nm node logic devices under the 1.3NA single exposure
conditions. The simulation and experimental results indicate that the minimum pitches should be
determined as 100nm for line pattern and 120nm for contact hole pattern, respectively. The isolated
feature needs SRAF to pull up the DOF margin. High density SRAM cell with 0.15um2 area is clearly
resolved across exposure and focus window. The 1.3NA scanner has sufficient focus and overlay stability.
There is no immersion induced defects.
We constructed hot spot management flow with a die-to-database inspection system that is required for both hot
spot extraction accuracy and short development turn-around-time (TAT) in low k1 lithography. The die-to-database
inspection system, NGR-2100, has remarkable features for the full chip inspection within reasonable operating time.
The system provided higher hot spot extraction accuracy than the conventional optical inspection tool. Also, hot spots
extracted by the system could cover all killer hot spots extracted by electrical and physical analysis. In addition, the new
hot spot extraction methodology employing the die-to-database inspection system is highly advantageous in that it
shortens development TAT by two to four months. In the application to 65nm node CMOS, we verified yield
improvement with the new hot spot management flow. Also, the die-to-database inspection system demonstrated
excellent interlayer hot spot extraction from the viewpoint of LSI fabrication.
This paper proposes a new virtual lithography system to improve the productivity of high-mix / low-volume production. In the case of the conventional technique, product mask and wafer are used to determine a focus-exposure-matrix (FEM) exposure condition.
The conventional technique is a "send-ahead" process involving exposure, metrology and data analysis that decreases productivity of manufacturing. In the case of low-volume/high-mix ASIC manufacturing, such a send-ahead process is particularly time-consuming and costly. Moreover, the exposure condition setting imposes a huge workload that is desirable to be avoided from the viewpoints of cost and TAT. Thus, a new methodology to determine exposure dose conditions for each mask in high-mix / low-volume production is required.
In this paper, we propose a virtual lithography system to eliminate send-ahead exposure. Firstly, to improve wafer CD prediction accuracy, we rebuild the system, thereby transforming it from a training-based system to a simulation-based system. To make simulation models, we use a golden mask, which is not a product mask. Secondly, exposure conditions are determined by considering 2D patterns including hotspot patterns. Thirdly, the lithography simulation is carried out for each exposure tool. Using the golden mask, we calibrate simulation models for each exposure tool1-3. Various patterns including hotspots likely to become fatal errors for circuit reliability due to process proximity effects are considered. The virtual system provides optimal exposure parameters according to product and layer, considering long-term variation of exposure tool conditions. By developing this system, TAT and cost for the determination of exposure parameters will be improved. Elimination of send-ahead wafers can reduce TAT from mask delivery to exposure condition setup in high-mix / low-volume production. Drastic cost reduction is realized in high-mix / low-volume production.
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