Silicon photonics is becoming a significant platform in high-bandwidth, low power device applications for HPC and cloud computing infrastructure. Its continuing push to displace incumbent copper and VCSEL technologies depends on the scaling potential of existing CMOS manufacturing processes. Central to this process is still the photomask, and its’ ability to accurately render design intent. However, processes and quality metrics that have been developed for electronics-centric photomasks do not translate directly to the needs of photonics-centric photomasks. This may lead to unconventional or non-intuitive choices for data rendering (fracture), mask pattern tooling (laser vs e-beam). Standard metrology (CD Uniformity, Localized LER) may not capture the essential elements that correlate mask pattern fidelity with waveguide signal loss. There are likely limits to a “blind translation” of IC-centric metrics to photonics-centric metrics. This paper will report on a collaborative effort to compare several photomask manufacturing approaches and their impact on photonics device performance (signal loss) for a common set of device structures. We will also explore the standard metrics applied to photomask quality and determine whether they correlate to waveguide performance, or whether different metrology approaches are required for vetting photonics-centric photomasks.
Microfabrication techniques, used widely for the construction of integrated circuits, are being used in an increasing variety of non-IC applications requiring features with curved shapes, such as the construction of photonics and microelectromechanical devices. Maintaining the fidelity of curved edges through the photomask fabrication process with tools originally designed to generate shapes with straight edges presents maskmakers with challenging issues of manufacturability and pattern fidelity. This paper will present and discuss various issues on the topic of photomask manufacturability for curvilinear structures; with recommendations for the design and layout of these structures to support photomask manufacturability while maintaining pattern fidelity.
This study quantifies the impact of systematic mask errors on OPC model accuracy and proposes a methodology to reconcile the largest errors via calibration to the mask error signature in wafer data. First, we examine through simulation, the impact of uncertainties in the representation of photomask properties including CD bias, corner rounding, refractive index, thickness, and sidewall angle. The factors that are most critical to be accurately represented in the model are cataloged. CD bias values are based on state of the art mask manufacturing data while other variable values are speculated, highlighting the need for improved metrology and communication between mask and OPC model experts. It is shown that the wafer simulations are highly dependent upon the 1D/2D representation of the mask, in addition to the mask sidewall for 3D mask models. In addition, this paper demonstrates substantial accuracy improvements in the 3D mask model using physical perturbations of the input mask geometry when using Domain Decomposition Method (DDM) techniques. Results from four test cases demonstrate that small, direct modifications in the input mask stack slope and edge location can result in model calibration and verification accuracy benefit of up to 30%. We highlight the benefits of a more accurate description of the 3D EMF near field with crosstalk in model calibration and impact as a function of mask dimensions. The result is a useful technique to align DDM mask model accuracy with physical mask dimensions and scattering via model calibration.
Computational lithography solutions rely upon accurate process models to faithfully represent the imaging system output for a defined set of process and design inputs. These models rely upon the accurate representation of multiple parameters associated with the scanner and the photomask. Many input variables for simulation are based upon designed or recipe-requested values or independent measurements. It is known, however, that certain measurement methodologies, while precise, can have significant inaccuracies. Additionally, there are known errors associated with the representation of certain system parameters. With shrinking total critical dimension (CD) control budgets, appropriate accounting for all sources of error becomes more important, and the cumulative consequence of input errors to the computational lithography model can become significant. In this work, we examine via simulation the impact of errors in the representation of photomask properties including CD bias, corner rounding, refractive index, thickness, and sidewall angle. The factors that are most critical to be accurately represented in the model are cataloged. CD bias values are based on state-of-the-art mask manufacturing data, and other variable changes are speculated, highlighting the need for improved metrology and communication between mask and optical proxmity correction model experts. The simulations are done by ignoring the wafer photoresist model and show the sensitivity of predictions to various model inputs associated with the mask. It is shown that the wafer simulations are very dependent upon the one-dimensional/two-dimensional representation of the mask, and for three-dimensional, the mask sidewall angle is a very sensitive factor influencing simulated wafer CD results.
Computational lithography solutions rely upon accurate process models to faithfully represent the imaging system output for a defined set of process and design inputs. These models rely upon the accurate representation of multiple parameters associated with the scanner and the photomask. Many input variables
for simulation are based upon designed or recipe-requested values or independent measurements. It is known, however, that certain measurement methodologies, while precise, can have significant inaccuracies. Additionally, there are known errors associated with the representation of certain system parameters. With shrinking total CD control budgets, appropriate accounting for all sources of error becomes more important, and the cumulative consequence of input errors to the computational lithography model can
become significant. In this work, we examine via simulation, the impact of errors in the representation of
photomask properties including CD bias, corner rounding, refractive index, thickness, and sidewall angle. The factors that are most critical to be accurately represented in the model are cataloged. CD bias values are based on state of the art mask manufacturing data and other variables changes are speculated, highlighting the need for improved metrology and communication between mask and OPC model experts. The simulations are done by ignoring the wafer photoresist model, and show the sensitivity of predictions to various model inputs associated with the mask. It is shown that the wafer simulations are very dependent upon the 1D/2D representation of the mask and for 3D, that the mask sidewall angle is a very sensitive factor influencing simulated wafer CD results.
Computational lithography solutions rely upon accurate process models to faithfully represent the imaging system output for a defined set of process and design inputs. These models, which must balance accuracy demands with simulation runtime boundary conditions, rely upon the accurate representation of multiple parameters associated with the scanner and the photomask. While certain system input variables, such as scanner numerical aperture, can be empirically tuned to wafer CD data over a small range around the presumed set point, it can be dangerous to do so since CD errors can alias across multiple input variables. Therefore, many input variables for simulation are based upon designed or recipe-requested values or independent measurements. It is known, however, that certain measurement methodologies, while precise, can have significant inaccuracies. Additionally, there are known errors associated with the representation of certain system parameters. With shrinking total CD control budgets, appropriate accounting for all sources of error becomes more important, and the cumulative consequence of input errors to the computational lithography model can become significant. In this work, we examine with a simulation sensitivity study, the impact of errors in the representation of photomask properties including CD bias, corner rounding, refractive index, thickness, and sidewall angle. The factors that are most critical to be accurately represented in the model are cataloged. CD Bias values are based on state of the art mask manufacturing data and other variables changes are speculated, highlighting the need for improved metrology and awareness.
Double Patterning Technology (DPT) is now considered as the mainstream technology for 32 nm node lithography. The main DPT processes have been developed according targeted applications: spacer and pitch splitting either by dual line or dual trench approaches. However, the successful implementation of DPT requires overcoming certain technical challenges in terms of exposure tool capability, process integration, mask performance and finally metrology (1, 2). For pitch splitting process, the mask performance becomes critical as the technique requires a set of two masks (3).
This paper will focus on the mask impact to the global critical dimension (CD) and overlay (OVL) errors for DPT. The mask long-distance and local off target CD variation and image placement were determined on DP features at 180 nm and 128 nm pitches, dedicated to 45 nm and 32 nm nodes respectively. The mask data were then compared to the wafer CD and OVL results achieved on same DP patterns.
Edge placement errors have been programmed on DP like-structures on reticle in order to investigate the offsets impact on CD and image placement. The CD lines increases with asymmetric spaces adjacent to the drawn lines for offsets higher than 12 nm, and then have been compared to the corresponding density induced by individual dense and sparse symmetric edges and have been correlated to the simulated prediction. The single reticle trans-X offsets were then compared to the impact on CD by OVL errors in the double patterning strategy.
Finally, the pellicle-induced reticle distortions impact on image placement errors was investigated (4). The mechanical performance of pellicle was achieved by mask registration measurements before and after pellicle removal.
The reticle contribution to the overall wafer CD and OVL errors budgets were addressed to meet the ITRS requirements.
A novel approach to improve the imaging of the critical magnetic pole structure in the disk drive read head is introduced. A 90-degree sub-resolution opening is added to an alternating aperture phase shift mask to reduce a strong proximity effect in the non-Manhattan tapered section, while maintaining the enhanced printability of the linear segment of the pole region.. Simulation indicates that this opening provides a method to correct the observed distortion in the printed edge without reducing the effectiveness of the altPSM character of the pole itself. We have designed test patterns with this concept and built photomasks to evaluate mask manufacturability and to empirically test the impact of the 90-degree window on final pattern fidelity on wafer. Preliminary results indicate positive correction effects, as well as some potential issues which may be resolved using additional, established correction approaches.
The data volumes of individual files used in the manufacture of modern integrated circuits have become unmanageable using existing data formats specifications. The ITRS roadmap indicates that single layer MEBES files in 2004 exceed 200 GB threshold, worst case. OASIS, the new stream format developed under the sponsorship of SEMI, has been approved in the industry-wide voting in June 2003. The new format that on average will reduce the file size by an order of magnitude, enables to streamline data flows and provides increased efficiency in data exchange. The work to implement the new format into software tools is in progress. This paper gives an overview on the new format, reports results on data volume reduction and is a report on the status and benefits the new format can deliver. A data flow relying on OASIS as the input and transfer format is discussed.
An investigation of the predominant industry approaches to transmission balance and phase error through pitch of Alternating Aperture Phase-Shifting Mask manufacturing approaches has been conducted. Previous theoretical studies have shown both clear pattern bias and phase error changes through pitch. These variations are significant for the Low K1 applications. Several approaches have been proposed and discussed in previous papers, including undercut, asymmetric pattern biasing, mask phase-only, dual trench, SCAA, and others. Although much of the discussion has focused on lithographic process performance, some of the constraints in the mask making infrastructure may differentiate between processes of similar performance. Two manufacturable approaches, wet etch undercut and asymmetric pattern biasing, have been studied by electromagnetic field simulation to explore the across pitch performance at 193nm. This has been compared to experimental measurement of photomasks measured with a 193 Zeiss AIMS (Aerial Image Microscope System). Both mask fabrication approaches are compared to the simulations. The performance of both mask approaches to pattern bias and phase error was evaluated, and the feasibility of through pitch correction and its impact on design and manufacturability of the photomask is discussed.
AAPSM masks require OPC correction through pitch in order to print a linear dark line response vs the design CDs. The masks also require correction for the clear intensity imbalance caused by the phased etched Qz wall edge. The clear intensity can be balanced by two approaches;(or a combination of the two) data biasing or wet undercut etching of the Qz etched opening. IC manufacturers would like to use one OPC model that will work for any mask fabrication approach. This paper shows that there is no OPC difference observed in either the aerial image or the printed image of several OPC learning patterns. The study includes CD through pitch for dense (1:1) L/S Patterns and Isolated Line CD vs line-space ratio. The images were analyzed for the dark line linearity, the clear CD balance though pitch, and the clear CD balance with focus (phase error effects -PES).
The OASIS format was designed to be a replacement for the GDSII stream format. Previous papers have reported that OASIS files can be 5-20X smaller than comparable GDSII files. This paper examines the storage capabilities of OASIS, as well as other benefits, in more detail. The primary focus of this study is on OASIS integers, deltas, point-lists, and its explicit support for rectangles & squares. We also show how the two OASIS integer types and four delta types can be implemented using a single core procedure.
The data volumes of individual files used in the manufacture of modern integrated circuits have become unmanageable using existing data formats specifications. The ITRS roadmap indicates that single layer MEBES files in 2002 reached the 50 GB range, worst case. Under the sponsorship of SEMI, a working group was formed to create a new format for use in describing integrated circuit layouts in a more efficient and extendible manner. This paper is a report on the status and potential benefits the new format can deliver.
It has long been understood that there is an image fidelity difference between the integrated circuit design pattern and the photomask made from that pattern, largely due to the finite spot size of pattern generators. Furthermore, there are known differences in photomask image fidelity (rounding, jogs, etc.) between e-beam and laser pattern generators. Using a novel technique developed by DuPont Photomasks, Inc. (DPI), actual photomask fidelity has been simulated from design data to produce a more true-to-life representation of the mask. We have performed analytical simulations and printed-wafer measurements on Cypress 100-nm technology designs to determine the differences and effects on optical proximity correction (OPC) of two types of pattern generators: 50 keV e-beam and DUV laser. Both JEOL 9000MV-II+ and ETEC ALTA 4000 images were simulated and saved in GDSII format (“mask-GDSII”). These new mask images were processed through standard lithography simulation software to predict the effects each mask writer has on localized optical proximity effects. Simulations were compared to printed wafer results. A detailed comparison of the accuracy of the mask-GDSII and original design GDSII is performed. Furthermore, comparison of 50 keV e-beam and DUV laser image fidelity is completed, and recommendations are made on how to correct OPC models for each type of photomask generator. Lastly, conclusions are drawn about the use of DUV laser and 50 keV e-beam photomasks.
Binary halftone chromeless PSM (CLM) can be described as a 100% transmission attenuated PSM (attPSM). The term 'binary halftone' refers to a novel OPC application to achieve the necessary CD control across the full feature-pitch range. We find that CLM is very complimentary -- with high numerical aperture (NA) and with off-axis illumination (OAI). In our wafer-printing experiment, we have achieved 70 nm through- pitch printing performance, using a KrF resist process. This was done in combination with a rule-based SB-OPC approach. At least 0.4 micrometer overlapped DOF with more than 6% exposure latitude has been attained for sub-100 nm printed features. For 2D complex patterns, we have observed a very strong optical proximity effect. CLM appears to be more sensitive to proximity effects, but less sensitive to lens aberration effects. Further experimentation and verification is required. Current mask-making processes appear to be capable of manufacturing CLM. We conclude that CLM has great potential to achieving production-worthy (lambda) /4 (or 0.2k1) lithography. The technology risk is neither in mask making nor in application software, but may be in reticle inspection and repair.
A simulation study has been performed to look at improving the imaging of a 130nm poly gate mask design. For this lithography process, we have chosen 6 percent attenuated PSM applied with scattering-bar optical proximity correction (SB-OPC) using 248 nm exposure wavelength. We compare the process window performance of off-axis illuminations (OAI) such as QUASAR and annular to a conventional on-axis illumination. Sampled lens aberrations were introduced to the simulation model to evaluate the impact of illumination settings. Simulations show benefits of combining SB-OPC technology with OAI on the performance of 130nm poly gate line features in the presence of known lens aberrations. For this simulation study, we have used our WaveMaster software tool to automate the SOLID-C simulation loops that includes multiple pre-selected line features form an actual poly gate mask design, five different lens aberration Zernike data sets, and three illumination settings.
An envisioned technology path to sub-0.1 micrometer process generations is first presented. OPC, PSM, and custom illumination apertures are all able to enhance the performance of the optical lithography. By integrating the use of these resolution enhancement technologies, it is possible to develop a production-worthy process that has sufficient overlapping process windows for all feature pitches. Critical dimension control is the key issue for sub-(lambda) process generations. The potential causes that can undermine CD control are discussed, and methods to minimize the problem are proposed. In addition to printing poly gate features, a method to print sub-(lambda) contact/via hole features is described. An outlook for meeting the technology challenges is discussed with conclusions.
Recent observations indicate that CD control for the 0.18 micrometer process generation using KrF exposure (k1 equals 0.41) could be sensitive to borderline detectable defect sizes (200 to 300 nm) on a 4X reticle. It is of interest to determine if these 'sub-killer' defect sizes can become process window limiting. It is also important to determine if CD error is sensitive to the interaction between defects and scattering bar (SB) OPC features. The experiment was based on a typical 0.18 micrometer process using the Defect Sensitivity Monitor (DSM) Reticle -- designed by MaskTools and manufactured by Photronics. Printed wafer data was presented previously on isolated feature cases. Here, data is presented on dense feature cases. In agreement with earlier isolated data, greater than 10% printed CD error was found for defects occurring on the main feature such as a 200 nm bump or a 250 nm divot on a 4X reticle. Greater than 6% of the exposure latitude can be lost due to plus or minus 50 nm (4X) mask feature width deviations.
As the semiconductor roadmap continues to require imaging of smaller features on wafers, we continue to explore new approaches in OPC strategies to enhance existing technology. Advanced reticle design, intended for printing sub-wavelength features, requires the support of very fine-increment biases on semi-densely-pitched lines, where the CD correction requires only a fraction of the spot size of an e-beam system. Halftone biasing, a new OPC strategy, has been proposed to support these biases on a raster-scan e-beam system without the need for a reduced address unit and the consequent write time penalty. The manufacturability and inspectability of halftone-biased lines are explored, using an OPC characterization reticle. Pattern fidelity is examined using both optical and SEM tools. Printed DUV resist line edge profiles are compared for both halftone and non-halftone feature edges. Halftone biasing was applied to an SRAM-type simulation reticle, to examine its impact on data volume, write time reduction, and printing performance.
Recent observations indicate that CD control for the 0.18 micrometers process generation using KrF exposure could be sensitive to borderline detectable defect sizes on a 4X reticle. It is of interest to determine if these 'sub- killer' defect sizes can become process window limiting. It is also important to determine if CD error is sensitive to the interaction between defects and scattering bar OPC features. The experiment was based on a typical 0.18 micrometers process using the Defect Sensitivity Monitor reticle - designed by MicroUnity and manufactured by Photronics. Only isolated features were investigated in this work. Greater than 10 percent printed CD error was found for defects occurring on the main feature such as a 200 nm bump or a 250 nm divot on a 4X reticle. Greater than 6 percent of the exposure latitude can be lost due to +/- 50 nm mask feature width deviations. A 200 nm-chrome spot 4X-reticle defect located between a main feature and an SB can cause more than a 10 percent printed CD error. Defects occurring on scattering bars such as bump a d break types have less influence on the printed CD. The CD error is negligible for +/- 100 nm SB width variation on a 4X reticle.
As the semiconductor roadmap continues to require imaging of smaller feature son wafers, we continue to explore new approaches in OPC strategies to extend the lifespan of existing technology. In this paper, we study a new OPC technology, called halftone biasing, and its application on an OPC characterization reticle, designed by MicroUnity Systems Engineering, Inc. The RTP9 test reticle is the latest in a series of 'LineSweeper' characterization reticles. Each reticle contains a wide range of line width sand pitches, each with several alternative OPC treatments, including references cases, scattering bars, and fine biasing. One of RTP9's design requirements was to support very fine, incremental biases for densely-pitched lines. Ordinarily, this would dictate a reduced address unit and with it the costly penalty of a square-law increase in e- beam write time. RTP9 incorporates a new OPC strategy, called halftone biasing, which has been proposed to address this problem. Taking advantage of optical reduction printing, this technique applies a sub-resolution halftone screen to the edges of figures to accomplish fine biasing equivalent to using an address unit one-fourth of the size of the actual e-beam writing grid. The resulting edge structure has some of the characteristics of aggressive OPC structures, but can be used in areas where traditional scattering bars cannot be placed. The trade-off between the faster write times achieved and the inflation of pattern file size is examined. The manufacturability and inspectability of halftone-biased lines on the RTP9 test reticle are explored. Pattern fidelity is examined using both optical and SEM tools. Printed 0.18 micrometers DUV resist line edge profiles are compared for both halftone and non- halftone feature edges. The CD uniformity of the OPC features, and result of die-to-database inspection are reported. The application of halftone biasing to real circuits, including the impact of data volume and saved write time, is also discussed.
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