KEYWORDS: Optical alignment, Electron beam direct write lithography, Electron beams, Overlay metrology, Control systems, Semiconducting wafers, Metals, Back end of line, Backscatter, Electron beam lithography
Techniques to appropriately control the key factors for a character projection (CP) based electron beam direct writing technology for mass production are shown and discussed. In order to achieve accurate CD control, the CP technique using the master CP is adopted. Another CP technique, the Packed CP, is used to obtain suitable shot count. For the alignment on the some critical layers which normally have an even surface, the process removing SiO2 material filled in the alignment marks is added and then the alignment marks can be detected using electron beam. The proximity effect correction using the simplified electron energy flux model and the hybrid exposure are used to obtain enough process margins. As a result, the sufficient CD accuracy, overlay accuracy, and yield are obtained on the 65 nm node device. Due to the proper system control, more than 10,000 production wafers have been successfully exposed so far without any major system downtime. It is shown that those techniques can be adapted to the 32 nm node production with slight modifications. It is expected that by using the Multi Column Cell exposure method, those techniques will be applicable to the rapid establishment for the 14 nm node technology.
We propose an advanced proximity effect correction method, in which all patterns of various sizes are written by
character projection (CP) method, and the dose modulation and the auxiliary shot generation are performed using
multiple area density maps with different mesh sizes according to the range of electron scatterings. We investigated the
possibility that all patterns of various sizes could be written by using small number of CP characters of a single line with
fixed width, which is called the "master-CP". We then estimated the range of the designed line width that can be
supported by a master-CP and the number of master-CPs which are needed in order to support all patterns of various
sizes. We found that only 5-7 master-CPs are required in terms of the dose margin, the rate of increase in the correction
dose caused by using the master-CP of different width from the design pattern and the shot positioning error, and they
have a low impact on the CP mask. Moreover, we estimated the effect of auxiliary shots on the throughput for 14 nm
node technology. The percentage of auxiliary shots in the exposure time was less than 12.1%, even though a test pattern
data was made by shrinking a 65 nm node logic LSI where the layout did not repeat very regularly. Therefore, as the
layout becomes regularly-repeated to 14 nm node, the effect of the auxiliary shots would not be a dominant factor for the throughput.
We investigated a high-resolution chemically amplified resist for introducing a multi-column cell electron-beam directwriting
system into the manufacturing of sub-14 nm technology node LSIs. The target of total blur, which leads to an
exposure latitude above 10%, is less than 13.6 nm for 14 nm logic node LSIs. We divided the total blur into three terms,
forward-scattering, electron-beam and resist. At a 40 nm-thick resist, the forward-scattering blur was calculated as 1.0
nm in lithography simulation, and beam blur was estimated to be 7.1 nm from the patterning results of hydrogen
silsesquioxane. We found that there is a proportional relation between resist blur and acid diffusion length by using a
new evaluation method that uses a water-soluble polymer. By applying a chemically amplified resist with a short acid
diffusion length, resist blur decreased to 14.5 nm. Even though total blur is still 16.2 nm, we have already succeeded in
resolving 20 nm line and space patterns at an exposure dose of 79.6 μC/cm2.
KEYWORDS: Electron beam direct write lithography, Optical alignment, Electron beams, Control systems, Semiconducting wafers, Overlay metrology, Metals, Photoresist processing, Backscatter, Electron beam lithography
Techniques to appropriately control the key factors for a character projection (CP) based electron beam direct writing
(EBDW) technology for mass production are shown and discussed. In order to achieve accurate CD control, the CP
technique using the master CP is adopted. Another CP technique, the Packed CP, is used to obtain suitable shot count.
For the alignment on the some critical layers which have the normally an even surface, the alignment methodology differ
from photolithography is required. The process that etches the SiO2 material in the shallow trench isolation is added and
then the alignment marks can be detected using electron beam even at the gate layer, which is normally on an even
surface. The proximity effect correction using the simplified electron energy flux model and the hybrid exposure are used
to obtain enough process margins. As a result, the sufficient CD accuracy, overlay accuracy, and yield are obtained on the
65 nm node device. The condition in our system is checked using self-diagnosis on a regular basis, and scheduled
maintenances have been properly performed. Due to the proper system control, more than 10,000 production wafers have
been successfully exposed so far without any major system downtime. It is shown that those techniques can be adapted
to the 32 nm node production with slight modifications. For the 14 nm node and beyond, however, the drastic increment
of the shot count becomes more of a concern. The Multi column cell (MCC) exposure method, the key concept of which
is the parallelization of the electron beam columns with a CP, can overcome this concern. It is expected that by using the
MCC exposure system, those techniques will be applicable to the rapid establishment for the 14 nm node technology.
The computer cost for mask data processing grows increasingly more expensive every year.
However the Graphics Processing Unit (GPU) has evolved dramatically. The GPU which
originally was used exclusively for digital image processing has been used in many fields of
numerical analysis. We developed mask data processing techniques using GPUs together with
distributed processing that allows reduced computer costs as opposed to a distributed processing
system using just CPUs.
Generally, for best application performance, it is important to reduce conditional branch
instructions, to minimize data transfer between the CPU host and the GPU device, and to optimize
memory access patterns in the GPU. Hence, in our optical proximity correction (OPC), the light
intensity calculation step, that is the most time consuming part of this OPC, is optimized for GPU
implementation and the other inefficient steps for GPU are processed by CPUs . Moreover, by
fracturing input data and balancing a computational road for each CPU, we have put the powerful
distributed computing into practice.
Furthermore we have investigated not only the improvement of software performance but also how
to best balance computer cost and speed, and we have derived a combination of the CPU hosts and
the GPU devices to maximize the processing performance that takes computer cost into account .
We have also developed a recovery function that continues OPC processing even if a GPU breaks
down during mask data processing for a production. By using the GPUs and distributed
processing, we have developed a mask data processing system which reduces computer cost and has
high reliability.
It is commonly known that maskless lithography is the most effective technology to reduce costs and shorten the time
need for recent photo-mask making techniques. In mass production, however, lithography using photo-masks is used
because that method has high productivity. Therefore a solution is to use maskless lithography to make prototypes and
use optical lithography for volume production. On the other hand, using an exposure technology that is different from
that used for mass production causes different physical phenomena to occur in the lithography process, and different
images are formed. These differences have an effect on the characteristics of the semiconductor device being made. An
issue arises because the chip characteristics are different for the sample chip and the final chip of the same product. This
issue also requires other processes to be changed besides switching to the lithography process. In our previous paper, we
reported on new developments in an electron-beam exposure data-generating system for making printed images of a
different exposure source correspond to each other in lithographic printing systems, which are electron beam lithography
and photolithography. In this paper, we discuss whether the feasibility of this methodology has been demonstrated for
use in a production environment. Patterns which are generated with our method are complicated. To apply the method to
a production environment we needed a breakthrough, and we overcame some difficult issues.
KEYWORDS: Lithography, Critical dimension metrology, Chemical mechanical planarization, Monte Carlo methods, Multilayers, Semiconducting wafers, Backscatter, Model-based design, Scattering, Systems modeling
In the high-energy electron-beam lithography, proximity effects caused by the multilayer structure including heavy-metal materials are crucial for the resist patterning. The proximity effect depends not only on the pattern arrangement in the underlying layers but also on the critical dimension (CD) variation of patterned metal in the underlying layers and the chemical-mechanical polishing (CMP) non-uniformity among chips on a wafer. This paper proposes a novel lithography verification method based on the SEEF model, where the backscattering deposited energy intensity distribution to the resist is calculated by the mapping of transmitted electron energy flux and reflected electron energy flux in the multilayer structure. The verification method provides the capability of CD error prediction considered the proximity effect caused by the multilayer structure.
Local flare is caused by scattered light from lens surfaces, and it causes the printed line width to vary or degrades printing accuracy. Consequently, local flare must be taken into account when manufacturing IC devices that use lithography generations of less than 90 nm. In particular, an OPC (Optical Proximity Correction) tool with the ability to compensate local flare effects is required to maintain a high degree of printing accuracy. For model-based OPC to work properly, the predicted line width or shape given by a simulator should show good agreement with experimental results. Local flare intensity is calculated from the optical intensity in the absence of local flare, in order to take diffraction effects into account. An aerial image considering local flare effects is given simply by the sum of optical intensity and local flare intensity. To account for local flare effects in a practical manner, the local flare intensity is converted into a variation in the threshold for OPC/DRC (Design Rules Checking) that predicts the desired shape. This paper describes the impact of local flare, the simulation model including local flare effects, and its results. The simulation results show good agreement with the experimental results, indicating that effective OPC/DRC using this method is possible.
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