A low-loss RF package has been realized using silicon- micromachining technique. As the frequency of the device increases, the loss caused by packaging increases. Therefore, low loss high frequency packaging is needed. For frequency above 10GHz, a metal package is used but a metal package has spurious resonance caused by interaction between radiation of RF circuits and cavity geometry. To suppress spurious resonance, microwave absorbers are deposited inside the metal package; it is very hard to process with these materials in microscale. In this work, high resistivity silicon is simulated as a high frequency packaging material, and is realized using silicon deep etching process. And metal-filled thorough-hole via is formed to provide surface mount type interconnection using sandblast and copper electroplating process. The silicon package has reflection loss of 15dB, insertion loss of 0.7db from 500MHz up to 40GHz region.
Area-varying tunable MEMS (MicroElectroMechanical Systems) capacitor with 608 comb fingers is developed. The 6 um-thick single crystal silicon MEMS structure is bonded to the pyrex glass substrate using the glass-silicon anodic bonding technique and chemical mechanical polish to make the designed capacitor. The pyrex glass is used as a substrate instead of the silicon for reducing the RF losses through the substrate. The measured capacitor shows the nominal capacitance of 1.4 pF, Q-factor of 4 at 1 GHz. The capacitor model is also developed and proved by Serenade software of Ansoft Corporation.
A Solenoid-type Inductors have been realized using electroplating technique mainly used for 2 Ghz band CMOS RF VCO applications. The integrated spiral inductor has low Q factor due to substrate loss and skin effects. And it also occupies large area compared to solenoid-type inductor. The direction of flux of the solenoid-type inductor is parallel to the substrate, which can lower substrate loss and other interference with integrated passive components. In this research, Solenoid-type inductors are simulated and modeled as equivalent circuit for CMOS RF VCO based on extracted S- parameters. The electroplated solenoid-type inductors are fabricated on both a standard silicon substrate and glass substrate by thick PR photolithography and copper electroplating. The achieved inductance varies range from 1 nH to 5 nH, and maximum Q factor over 10. The inductors are scheduled to be integrated on CMOS RF VCO with RF MEMS capacitor for future.
An accelerometer array that is a new concept for inertial sensing paradigm is presented. A surface micromachining technology with 6 micrometers -thick polycrystalline silicon was used to fabricate the array and dichlorodimethylsilane grafting as a new anti-stiction method was used to perfectly release 36 accelerometer cells. Test result show the dynamic range of +/- 30G with 1 percent non-linearity and 2.5 mG noise equivalent level. The XL-array was composed of 36 sensing capacitors of the accelerometer cells that are connected in parallel. So the total capacitance in the XL- array was the capacitance of unit cell multiplied by the number of the accelerometer cell.Lager capacitance change is required to obtain a high sensitivity and SNR. This multiple cell structure could provide redundancy for low-yield manufacturing. The cell structures can be easily scaled for spring stiffness and mass to increase the resonant frequency and operating bandwidth. This array-typed structure also gives less sensitivity to residual stress and stress gradient than larger single mass structure. Higher performance can be achieved by making of large array.
We use the highly sensitive chemically amplified resist to obtain the high resolution and sensitivity in deep sub- micron region. We analyze the edge profiles and performances of resist by using the Electron-beam Lithography simulator (ELIS) and experiments. We mainly characterize the trend of resist profiles to measure the variation of wall angle, sensitivity, contrast, and solubility. In the simulation, development model for CAR is optimized to express the developed profiles of highly sensitive resist with high solubility and to have a good agreement with resist profiles in the electron beam lithography. From our results, we understand that resist edge profile depends on the solubility, sensitivity, and contrast of resist in the developer and got the high resolution to 0.15 micrometers line and space patterns using Leica EBMF 10.5 Gaussian beam. Finally, the ELIS simulator is useful in optimizing the deep sub- micron process.
KEYWORDS: Monte Carlo methods, Electron beam lithography, Photoresist processing, Optical simulations, Polymethylmethacrylate, Deep ultraviolet, Electron beams, Scattering, 3D modeling, Lithography
This paper reports the initial results and experimental approach method on three-dimensional simulation and modeling of electron beam lithography in the 0.2micrometers line and space patterns. We studied the electron scattering distribution in the resist, the energy distribution of patterns and the developement mechanism for profile formation. The simplified string model of three-dimensions is used to remove the pattern exposed by direct writing. Development rate is experimentally decided as the dependency of dose, development time, and resisit characteristics in the solvents to delineate 0.2micrometers /0.3micrometers line and space patterns for negative and positive resist. As a result, we obtained the optimum resist profile of 0.2micrometers line and space patterns with various forms as the variance of exposure energy and develop time. Also, we can see the proximity effects in generating pattern. These results agree with actual process for deep sub-micron patterns.
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