Prof. Lawrence Pileggi Profile

Prof. Lawrence Pileggi

Tanoto Professor of Electrical and Computer Engg at Carnegie Mellon Univ

SPIE Involvement:

Author

SPIE Press Book | 8 January 2016

Design Technology Co-Optimization in the Era of Sub-Resolution IC Scaling

Lars Liebmann, Lawrence Pileggi, Kaushik Vaidyanathan

KEYWORDS: Optical lithography, Logic, Computer aided design, Manufacturing, Metals, Lithography, Photomasks, Diffusion, Transistors

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Design Technology Co-Optimization in the Era of Sub-Resolution IC Scaling

SPIE Journal Paper | 30 December 2014

Exploiting sub-20-nm complementary metal-oxide semiconductor technology challenges to design affordable systems-on-chip

Kaushik Vaidyanathan, Qiuling Zhu, Lars Liebmann, Kafai Lai, Stephen Wu, Renzhi Liu, Yandong Liu, Andzrej Strojwas, Larry Pileggi

JM3, Vol. 14, Issue 01, 011007, (December 2014) https://doi.org/10.1117/12.10.1117/1.JMM.14.1.011007

KEYWORDS: Computer aided design, Manufacturing, System on a chip, Logic, Optical lithography, Standards development, Analog electronics, Semiconductors, CMOS technology

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SPIE Journal Paper | 3 October 2014

Design implications of extremely restricted patterning

Kaushik Vaidyanathan, Renzhi Liu, Lars Liebmann, Kafai Lai, Andrzej Strojwas, Larry Pileggi

JM3, Vol. 13, Issue 03, 031309, (October 2014) https://doi.org/10.1117/12.10.1117/1.JMM.13.3.031309

KEYWORDS: Optical lithography, System on a chip, Optical design, Computer aided design, Lithography, Analog electronics, Manufacturing, Logic, Transistors

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Proceedings Article | 29 March 2013 Paper

Rethinking ASIC design with next generation lithography and process integration

Kaushik Vaidyanathan, Renzhi Liu, Lars Liebmann, Kafai Lai, Andrzej Strojwas, Larry Pileggi

Proceedings Volume 8684, 86840C (2013) https://doi.org/10.1117/12.2014374

KEYWORDS: Computer aided design, Analog electronics, Standards development, Optical lithography, Optical design, Manufacturing, Lithography, Transistors, Logic

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Proceedings Article | 15 March 2012 Paper

Local loops for robust inter-layer routing at sub-20 nm nodes

Wenbin Huang, Daniel Morris, Neal Lafferty, Lars Liebmann, Kaushik Vaidyanathan, Kafai Lai, Larry Pileggi, Andrzej Strojwas

Proceedings Volume 8327, 83270D (2012) https://doi.org/10.1117/12.916290

KEYWORDS: Metals, Lithography, Solids, Failure analysis, Manufacturing, Resistance, SRAF, Capacitance, Electronic design automation, Yield improvement

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Proceedings Article | 15 March 2012 Paper

Design and manufacturability tradeoffs in unidirectional and bidirectional standard cell layouts in 14 nm node

Kaushik Vaidyanathan, Siew Hoon Ng, Daniel Morris, Neal Lafferty, Lars Liebmann, Mitchell Bender, Wenbin Huang, Kafai Lai, Larry Pileggi, Andrzej Strojwas

Proceedings Volume 8327, 83270K (2012) https://doi.org/10.1117/12.916104

KEYWORDS: Manufacturing, Back end of line, Standards development, Metals, Design for manufacturability, Lithography, Logic, Optical lithography, Front end of line, Transistors

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Proceedings Article | 4 April 2011 Paper

Performance and manufacturability trade-offs of pattern minimization for sub-22nm technology nodes

Vyacheslav Rovner, Tejas Jhaveri, Daniel Morris, Andrzej Strojwas, Larry Pileggi

Proceedings Volume 7974, 79740I (2011) https://doi.org/10.1117/12.879514

KEYWORDS: Logic, Manufacturing, Silicon, Source mask optimization, Optical lithography, Multiplexers, Neodymium, Connectors, Chemical mechanical planarization, Radon

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Proceedings Article | 3 April 2010 Open Access

Application of the cost-per-good-die metric for process design co-optimization

Tejas Jhaveri, Umut Arslan, Vyacheslav Rovner, Andrzej Strojwas, Larry Pileggi

Proceedings Volume 7641, 764104 (2010) https://doi.org/10.1117/12.846556

KEYWORDS: Lithography, Process engineering, Manufacturing, Design for manufacturability, Current controlled current source, Semiconductors, Semiconducting wafers

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Proceedings Article | 3 April 2010 Paper

Demonstrating the benefits of template-based design-technology co-optimization

Lars Liebmann, Jason Hibbeler, Nathaniel Hieter, Larry Pileggi, Tejas Jhaveri, Matthew Moe, Vyacheslav Rovner

Proceedings Volume 7641, 76410R (2010) https://doi.org/10.1117/12.848244

KEYWORDS: Logic, Manufacturing, Yield improvement, Logic devices, Legal, Semiconductors, Design for manufacturability, Lithography, Model-based design, Process modeling

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Proceedings Article | 23 September 2009 Paper

Economic assessment of lithography strategies for the 22nm technology node

Tejas Jhaveri, Andrzej Strojwas, Larry Pileggi, Vyacheslav Rovner

Proceedings Volume 7488, 74882Y (2009) https://doi.org/10.1117/12.837240

KEYWORDS: Lithography, Semiconducting wafers, Source mask optimization, 193nm lithography, Optical lithography, Manufacturing, Dysprosium, Electron beam lithography, Double patterning technology, Process modeling

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Proceedings Article | 16 March 2009 Paper

OPC simplification and mask cost reduction using regular design fabrics

Tejas Jhaveri, Ian Stobert, Lars Liebmann, Paul Karakatsanis, Vyacheslav Rovner, Andrzej Strojwas, Larry Pileggi

Proceedings Volume 7274, 727417 (2009) https://doi.org/10.1117/12.814406

KEYWORDS: Optical proximity correction, Photomasks, Model-based design, Metals, Lithography, Manufacturing, Optical lithography, Double patterning technology, Inspection, Yield improvement

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Proceedings Article | 13 March 2009 Paper

Simplify to survive: prescriptive layouts ensure profitable scaling to 32nm and beyond

Lars Liebmann, Larry Pileggi, Jason Hibbeler, Vyacheslav Rovner, Tejas Jhaveri, Greg Northrop

Proceedings Volume 7275, 72750A (2009) https://doi.org/10.1117/12.814701

KEYWORDS: Logic, Metals, Lithography, Optical lithography, Design for manufacturing, Yield improvement, Model-based design, Diffusion, Transistors, Process modeling

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Proceedings Article | 7 March 2008 Paper

Enabling technology scaling with "in production" lithography processes

Tejas Jhaveri, Andrzej Strojwas, Larry Pileggi, Vyachelav Rovner

Proceedings Volume 6924, 69240K (2008) https://doi.org/10.1117/12.776484

KEYWORDS: Lithography, Metals, Front end of line, Optical lithography, Photomasks, Manufacturing, Optical design, Transistors, Standards development, Double patterning technology

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SPIE Journal Paper | 1 July 2007

Maximization of layout printability/manufacturability by extreme layout regularity

Tejas Jhaveri, Vyacheslav Rovner, Larry Pileggi, Andrzej Strojwas, Dipti Motiani, Veerbhan Kheterpal, Kim Yaw Tong, Thiago Hersan, Davide Pandini

JM3, Vol. 6, Issue 03, 031011, (July 2007) https://doi.org/10.1117/12.10.1117/1.2781583

KEYWORDS: Logic, Metals, Manufacturing, Lithography, Standards development, Silicon, Integrated circuit design, Design for manufacturability, Optical proximity correction, Resolution enhancement technologies

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Proceedings Article | 24 March 2006 Paper

Maximization of layout printability/manufacturability by extreme layout regularity

Tejas Jhaveri, Larry Pileggi, Vyacheslav Rovner, Andrzej Strojwas

Proceedings Volume 6156, 615609 (2006) https://doi.org/10.1117/12.659984

KEYWORDS: Logic, Metals, Manufacturing, Lithography, Silicon, Resolution enhancement technologies, Standards development, Design for manufacturability, Image quality, Optical proximity correction

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Showing 5 of 15 publications

Conference Committee Involvement (2)

Design for Manufacturability through Design-Process Integration VI

15 February 2012 | San Jose, California, United States

Design for Manufacturability through Design-Process Integration V

2 March 2011 | San Jose, California, United States

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