Dr. Laurent Pain Profile

Dr. Laurent Pain

Sustainable Electronic program director at CEA-LETI

SPIE Involvement:

Conference Program Committee | Author

Publications (65)

Proceedings Article | 9 April 2024 Presentation + Paper

Characterization and mitigation of local wafer deformations introduced by direct wafer-to-wafer bonding

Richard van Haren, Suwen Li, Mart Baars, Blandine Minghetti, Leon van Dijk, Ivanie Mendes, Karine Abadie, Marie-Line Pourteau, Gaëlle Mauguen, Michael May, Viorel Balan, Frank Fournel, Laurent Pain, Thomas Plach, Gernot Probst, Markus Wimplinger

Proceedings Volume 12956, 1295606 (2024) https://doi.org/10.1117/12.3010477

KEYWORDS: Wafer bonding, Semiconducting wafers, Distortion, Scanners, Silicon, Optical alignment, Deformation, Adhesion, Etching, Metrology

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A new application in the semiconductor industry that received quite some traction the past few years is bringing the transistor power delivery network to the backside of the wafer. The big gain of this change is that it frees up real estate on the frontside of the wafer, enabling a further increase of the transistor density. This so-called Back-Side Power Delivery Network (BS-PDN) application is quite challenging since it requires a direct wafer-to-wafer bonding process module. To get access to the transistor from the backside, a device wafer needs to be flipped and bonded to a carrier wafer followed by an annealing step. After these processing steps, the original substrate of the device wafer is removed by grinding and etch steps. This will enable access to the transistors from the backside of the wafer. The wafer processing continues by conventional layer deposition, lithography and etch steps, this time on the flipped wafer. Unfortunately, the bonding process module that includes the actual direct wafer-to-wafer bonding step itself, will also introduce a distortion in the device layer that has been transferred to the carrier wafer. Since the on-product overlay requirement for the first exposed layer on the backside to one of the front-side layers is tight (<10-nm today and <<5-nm in the foreseeable future), a deep understanding of the origin of the distortion fingerprint after bonding is required. In our previous work, we presented a method to isolate the distortion fingerprint due to bonding from the remaining other overlay contributors. The fingerprint we observed after linear corrections had a typical magnitude ranging from 50 to 80-nm. A clear 4-fold symmetry was observed that could be attributed to the crystal orientation of the (100) silicon substrate. We demonstrated that the scanner wafer alignment model is very capable of correcting the global 4-fold wafer distortion fingerprint. Residual levels of less than ~15-nm were shown. These residuals could be further reduced by applying a correction per exposure (CPE) recipe. We showed that performance levels of less than ~6-nm (99.7%) and ~10-nm (max) could be achieved after a 33-parameter per exposure field self-correction. The resulting wafer plots nicely revealed how to improve the overlay performance further. An increased level of residuals was found in the wafer center and at the wafer edge. In the current paper, we build upon our previous work and continue the investigation on the remaining overlay contributors that were identified previously. This time, the focus will be on the local wafer deformations that are visible after the direct wafer-to-wafer bonding step. By local we mean the distortions that manifest themselves over a very short spatial range. These local distortions cannot easily be corrected by the scanner and are typically present close to the wafer center and the wafer edge. We know that the local wafer deformation close to the wafer center is caused by the bonding pin that initiates the bond wave. To characterize the center distortion signature, we varied many experimental parameters to see the impact. We will show the impact of the die layout, the rotation of the top wafer by a 45-degrees, wafer surface properties, and substrate choice of the carrier wafer. The latter is interesting, we evaluated both (100) and (111) carrier wafers. Although the prime focus will be to improve the overlay performance on the center of the wafer, we monitor the impact of the experimental settings on the wafer edge and remaining part of the wafer as well. We present a path forward to mitigate the local distortions such that they will not be blocking for high volume production.

SPIE Journal Paper | 2 December 2023 Open Access

Special Section Guest Editorial: Direct Write Lithography

Stephen Renwick, Laurent Pain

JM3, Vol. 22, Issue 04, 041401, (December 2023) https://doi.org/10.1117/12.10.1117/1.JMM.22.4.041401

KEYWORDS: Direct write lithography, Electron beam direct write lithography, Semiconducting wafers, Lithography, Photomasks, Vestigial sideband modulation, Semiconductors, Wafer level optics, Universities, Soldiers

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SPIE Journal Paper | 12 June 2023

Electron beam direct write lithography: the versatile ally of optical lithography

Fabien Laulagnet, Jacques-Alexandre Dallery, Laurent Pain, Michael May, Béatrice Hémard, Franck Garlet, Isabelle Servin, Chiara Sabbione

JM3, Vol. 22, Issue 04, 041404, (June 2023) https://doi.org/10.1117/12.10.1117/1.JMM.22.4.041404

KEYWORDS: Electron beam direct write lithography, Lithography, Semiconducting wafers, Electron beam lithography, Optical lithography, Optical alignment, Photoresist processing, Design and modelling, Overlay metrology, Silicon

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Proceedings Article | 1 May 2023 Presentation + Paper

E-beam direct write lithography: the versatile ally of optical lithography

Fabien Laulagnet, Jacques-Alexandre Dallery, Laurent Pain, Michael May, Beatrice Hémard, Franck Garlet, Isabelle Servin, Chiara Sabbione

Proceedings Volume 12497, 1249706 (2023) https://doi.org/10.1117/12.2658273

KEYWORDS: Electron beam direct write lithography, Lithography, Semiconducting wafers, Electron beam lithography, Optical alignment, Overlay metrology, Optical lithography, Design and modelling, Photoresist processing, Deep ultraviolet

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Proceedings Article | 27 April 2023 Poster + Paper

Enabling layer transfer and back-side power delivery network applications by wafer bonding and scanner correction optimizations

Richard van Haren, Suwen Li, Blandine Minghetti, Leon van Dijk, Klaas Brantjes, Frank Fournel, Gaëlle Mauguen, Ivanie Mendes, Céline Lapeyre, Marie-Line Pourteau, Michael May, Laurent Pain, Karine Abadie, Thomas Plach, Markus Wimplinger

Proceedings Volume 12496, 124962C (2023) https://doi.org/10.1117/12.2657422

KEYWORDS: Wafer bonding, Semiconducting wafers, Scanners, Silicon, Distortion, Optical alignment, Transistors, Oxides, Crystals, Etching

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Apart from the ever-continuing lateral scaling in the xy-plane to increase the transistor density, additional new concepts find their way to the semiconductor industry too. These concepts are based on making more use of the third dimension. One relatively simple idea would be to create a second layer of transistors to double the transistor density. However, the material requirements are high and the quality of the layer deposition by conventional Chemical Vapor Deposition (CVD) techniques is insufficient. Another application to free up real estate, enabling a smaller cell size and hence an increased transistor density, is to power-up the transistors from the backside. The power rails for logic devices are historically defined in the first Metal layer and consume quite some space. Bringing the power rails to the backside will free up space. However, access to the transistor layer from the backside of the wafer is far from trivial due to the presence of a 775-μm thick silicon substrate. The answer to the challenges mentioned above is wafer-to-wafer direct bonding. Although this technique is not new and already widely used in the semiconductor industry to manufacture CMOS Image Sensors (CIS), it currently finds its way to the high-end logic markets. In case of layer transfer, a crystalline silicon layer is created by bonding a Silicon-On- Insulator (SOI) wafer to the already existing device wafer. After the bonding step, the substrate of the SOI wafer will be removed leaving the crystalline silicon layer behind. Access to the transistor layer from the wafer backside can be enabled by wafer-to-wafer bonding as well. To this end, a completed device wafer will be bonded to an (un-patterned) carrier wafer. The substrate of the original device wafer will be removed, enabling access from the backside. Wafer-towafer bonding applications can only be enabled in case the induced wafer deformations are low or when they can easily be corrected during the subsequent exposures on the scanner. At CEA-Leti, a dedicated test vehicle process flow has been developed to characterize the wafer bonding-induced distortion fingerprints for both the layer transfer and the backside power delivery network applications. The wafer process flow has been simplified without losing the industry relevant on-product overlay challenges. Wafers have been created to enable an extremely dense characterization of the wafer bonding induced fingerprint. The methodology we applied enables us to isolate the wafer bonding induced distortion fingerprint, something that is difficult to do in a production environment. The Back-Side Power Delivery Network (BS-PDN) application is the most challenging one. The initial raw measured wafer distortion fingerprints are around 60 to 80-nm. These numbers can already be easily brought down by scanner corrections to ~15-nm (mean+3σ) without too much effort. However, these numbers are too large for the 2-nm technology node and beyond, and further improvement is required. The goal of this paper is to present the path forward to bring the bonding induced wafer distortion levels to 10-nm and below. We show the capability of the latest and greatest EVG bonding tool hardware and recipe settings available at the time of running the experiments in combination with the correction capability an ASML 0.33NA scanner.

Proceedings Article | 16 August 2019 Presentation

Performance validation of Mapper’s FLX-1200 (Conference Presentation)

Marco Wieland, Jonathan Pradelles, Stéfan Landis, Laurent Pain, Guido Rademaker, Isabelle Servin, Guido De Boer, Pieter Brandt, Remco J. Jager, Stijn W. H. Steenbrink

Proceedings Volume 10958, 109580I (2019) https://doi.org/10.1117/12.2514920

KEYWORDS: Wafer-level optics, Semiconducting wafers, Critical dimension metrology, Electron beams, Optical alignment, Maskless lithography, Switching, Electron beam lithography, Standards development, Lithography

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Mapper has installed its first product, the FLX–1200, at CEA-Leti in Grenoble (France). This is a maskless lithography system, based on massively parallel electron-beam writing with high-speed optical data transport for switching the electron beams. The FLX-1200, containing 65,000 parallel electron beams, has a 1 wph throughput at 300 mm wafers and is capable of patterning any resolution and any different type of structure all the way down to 28 nm node patterns. The system has an optical alignment system enabling mix-and-match with optical 193 nm immersion system using standard NVSM marks. Mapper Lithography and CEA-Leti are collaborating to develop turnkey solution for specific applications. In figure 1 the basic operation principle of the Mapper technology is shown. The electron optics have no central crossovers making them intrinsically insensitive to Coulomb forces (electron repulsion). The electron optics are modular and much cheaper than high-NA DUV optics, and can be replaced or upgraded in the field. The wafer exposure happens one column of fields at a time and always in the same direction. There is no need to meander. The focus and leveling is performed during stage fly-back to reduce metrology overhead. Each column of fields is aligned separately, with dedicated alignment targets. Figure 1, Basic operation of the Mapper technology. In figure 2 the way the beams are distributed over the electron optics slit is shown. The writing strategy is as follows: - There are up to 5 slits, staggered in X direction for reasons of wafer coverage. The approach is roughly analogous to an inkjet printer - Each slit area consists of 204 x 13 individual groups of beamlets, organized in a hexagonal array. - All beamlets are simultaneously horizontally deflected over a range of 2µm while the wafer is scanned vertically. - Each group comprises 49 individual beamlets (7x7). Each of the 49 beamlets can independently be switched on and off during exposure. - Each beamlet results in a Gaussian spot on the wafer with 25 nm FW50 diameter (10.6nm 1). - Total beamlet count will therefore equal 5 x 204x13 x 49 = 649,740. In the FLX-1200 and FLX-1300 the central 10% are used (one half slit area): 65,000 A more detailed description of the principles of operation is given in [2]. Figure 2,Distribution of the beams over the electron optics slit. The focus of presentation will be the reporting of the performance achieved of the tool installed at CEA-Leti during endurance runs in full tool configuration. This includes status of: - Exposure throughput - Achieved resolution and CD uniformity - Stitching performance - Matched Machine Overlay - Tool availability and uptime Also the different application areas for such a maskless system are discussed. In figure 3 a preview of a CD uniformity measurement result is shown. On a 300 mm wafer fields of 5mm x 5mm have been exposed containing 60nm dense lines and spaces. The main source of CD variation is caused by differences between the groups of beamlets. To measure this variation we have taken 824 SEM images, each taken of a pattern written by a different beam group. The result is shown in figure 3. The variation is 8nm 3s, and follows a Gaussian distribution of 6nm 3s. Figure 3, Distribution of 824 CD measurements results on 60nm dense lines and spaces

Proceedings Article | 26 March 2019 Paper

Spacer patterning lithography as a new process to induce block copolymer alignment by chemo-epitaxy

A. Paquet, A. Le Pennec, A. Gharbi, T. Giammaria, G. Rademaker, M.-L. Pourteau, D. Mariolle, C. Navarro, C. Nicolet, X. Chevalier, K. Sakavuyi, L. Pain, P. Nealey, R. Tiron

Proceedings Volume 10958, 109580M (2019) https://doi.org/10.1117/12.2514960

KEYWORDS: Etching, Lithography, Optical lithography, Wet etching, HF etching, Critical dimension metrology, Silicon, System on a chip, Tin

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Proceedings Article | 26 March 2019 Paper

Evaluation of adhesion layers performances for soft UV nanoimprint lithography

F. Delachat, H. Teyssedre, L. Pain, X. Chevalier, Célia Nicolet, Christophe Navarro

Proceedings Volume 10958, 1095816 (2019) https://doi.org/10.1117/12.2515607

KEYWORDS: Semiconducting wafers, Nanoimprint lithography, Adhesives, Ultraviolet radiation, Silicon, Thin films, Etching, Coating

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Proceedings Article | 19 September 2018 Paper

Feasibility of monitoring a multiple e-beam tool using scatterometry and machine learning: stitching error detection

Guido Rademaker, Yoann Blancquaert, Thibault Labbaye, Lucie Mourier, Nivea Figueiro, Francisco Sanchez, Roy Koret, Jonathan Pradelles, Stéfan Landis, Stéphane Rey, Ronny Haupt, Barak Bringoltz, Michael Shifrin, Daniel Kandel, Avron Ger, Matthew Sendelbach, Shay Wolfling, Laurent Pain

Proceedings Volume 10775, 1077508 (2018) https://doi.org/10.1117/12.2326595

KEYWORDS: Machine learning, Scatterometry, Semiconducting wafers, Lithography, Metrology, Channel projecting optics, Wafer-level optics, Reflectance spectroscopy, Inverse optics, Electron beam direct write lithography, Maskless lithography

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Multiple electron beam direct write lithography is an emerging technology promising to address new markets, such as truly unique chips for security applications. The tool under consideration, the Mapper FLX-1200, exposes long 2.2 μm-wide zones called stripes by groups of 49 beams. The critical dimensions inside and the registration errors between the stripes, called stitching, are controlled by internal tool metrology. Additionally, there is great need for on-wafer metrology of critical dimension and stitching to monitor Mapper tool performance and validate the internal metrology. Optical Critical Dimension (OCD) metrology is a workhorse technique for various semiconductor manufacturing tools, such as deposition, etching, chemical-mechanical polishing and lithography machines. Previous works have shown the feasibility to measure the critical dimension of non-uniform targets by introducing an effective CD and shown that the non-uniformity can be quantified by a machine learning approach. This paper seeks to extend the previous work and presents a preliminary feasibility study to monitor stitching errors by measuring on a scatterometry tool with multiple optical channels. A wafer with OCD targets that mimic the various lithographic errors typical to the Mapper technology was created by variable shaped beam (VSB) e-beam lithography. The lithography process has been carefully tuned to minimize optically active systematic errors such as critical dimension gradients. The OCD targets contain horizontal and vertical gratings with a pitch of 100 nm and a nominal CD of 50 nm, and contain various stitching error types such as displacement in X, Y and diagonal gratings. Sensitivity to all stitching types has been shown. The DX targets showed non-linearity with respect to error size and typically were a factor of 3 less sensitive than the promising performance of DY targets. A similar performance difference has seen in nominally identical diagonal gratings exposed with vertical and horizontal lines, suggesting that OCD metrology for DX cannot be fully characterized due to lithography errors in gratings with vertical lines.

Proceedings Article | 19 September 2018 Paper

Performance validation of Mapper FLX-1200

Jonathan Pradelles, Yoann Blancquaert, Stefan Landis, Laurent Pain, Guido Rademaker, Isabelle Servin, Guido de Boer, Pieter Brandt, Michel Dansberg, Remco Jager, Jerry Peijster, Erwin Slot, Stijn Steenbrink, Marco Wieland

Proceedings Volume 10775, 1077507 (2018) https://doi.org/10.1117/12.2324054

KEYWORDS: Semiconducting wafers, Overlay metrology, Prototyping, Optical scanning, Scanning electron microscopy, Lithography, Line width roughness, Optical alignment, Electron beams, Silicon

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Proceedings Article | 22 March 2018 Presentation + Paper

Overlay and stitching metrology for massively parallel electron-beam lithography

Guido Rademaker, Jonathan Pradelles, Stéfan Landis, Stephane Rey, Anna Golotsvan, Anat Marchelli, Tal Itzkovich, Tetyana Shapoval, Ronny Haupt, Erwin Slot, Guido de Boer, Dhara Dave, Marco Wieland, Laurent Pain

Proceedings Volume 10585, 105850U (2018) https://doi.org/10.1117/12.2297535

KEYWORDS: Overlay metrology, Metrology, Electron beam lithography, Lenses, Distance measurement, Electron beams, Raster graphics, Semiconducting wafers, Time metrology, Process control

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Proceedings Article | 19 March 2018 Paper

Precise control of template affinity achieved by UV-assisted graphoepitaxy approach on silicon nanowires applications

P. Pimenta-Barros, G. Claveau, M. Argoud, Z. Chalupa, N. Allouti, C. Comboroure, G. Chamiot-Maitral, N. Posseme, L. Pain, R. Tiron, C. Navarro, C. Nicolet, I. Cayrefourcq

Proceedings Volume 10584, 105840C (2018) https://doi.org/10.1117/12.2297407

KEYWORDS: Etching, Silicon, Ultraviolet radiation, Directed self assembly, Polymethylmethacrylate, Scanning electron microscopy, Plasma, Nanowires, Line width roughness, Surface properties

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Proceedings Article | 19 March 2018 Presentation + Paper

Pillars fabrication by DSA lithography: material and process options

A. Gharbi, P. Pimenta-Barros, O. Saouaf, G. Reynaud, L. Pain, R. Tiron, C. Navarro, C. Nicolet, I. Cayrefourcq, M. Perego, F. Pérez-Murano, E. Amat, M. Fernández-Regúlez

Proceedings Volume 10586, 105860Q (2018) https://doi.org/10.1117/12.2297414

KEYWORDS: Polymethylmethacrylate, Picosecond phenomena, Directed self assembly, Annealing, Etching, Scanning electron microscopy, Dry etching, Silicon, Lithography, Plasma etching

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Proceedings Article | 19 March 2018 Presentation

Inorganic guiding template implementation for DSA contact hole shrink process (Conference Presentation)

Ahmed Gharbi, Florian DELACHAT, Patricia Pimenta-Barros, Gaëlle Chamiot-Maitral, Maxime Argoud, Celine Lapeyre, Laurent Pain, Christophe Navarro, Célia Nicolet, Ian Cayrefourcq, Raluca Tiron

Proceedings Volume 10584, 105840D (2018) https://doi.org/10.1117/12.2297422

KEYWORDS: Directed self assembly, Optical lithography, Critical dimension metrology, Silicon, Oxides, Semiconducting wafers, Semiconductors, Materials processing, Photomasks, Photoresist processing

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Proceedings Article | 19 March 2018 Presentation + Paper

Performance validation of Mapper's FLX-1200

Marco Wieland, Guido de Boer, Pieter Brandt, Michel Dansberg, Remco Jager, Jerry Peijster, Erwin Slot, Stijn Steenbrink, Yoann Blancquaert, Stefan Landis, Laurent Pain, Jonathan Pradelles, Guido Rademaker, Isabelle Servin

Proceedings Volume 10584, 105840G (2018) https://doi.org/10.1117/12.2300816

KEYWORDS: Semiconducting wafers, Line width roughness, Optical alignment, Overlay metrology, Electron beams, Electron beam lithography

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Proceedings Article | 27 April 2017 Presentation

Overlay performance assessment of MAPPER's FLX-1200 (Conference Presentation)

Ludovic Lattard, Isabelle Servin, Jonathan Pradelles, Yoann Blancquaert, Guido Rademaker, Laurent Pain, Guido de Boer, Pieter Brandt, Michel Dansberg, Remco J. Jager, Jerry J. Peijster, Erwin Slot, Stijn W. H. Steenbrink, Niels Vergeer, Marco Wieland

Proceedings Volume 10144, 101440N (2017) https://doi.org/10.1117/12.2260878

KEYWORDS: Semiconducting wafers, Lithography, Electron beam lithography, Photomasks, Switching, Electron beams, Lithographic illumination, Integrated optics, Optical alignment, Wafer-level optics

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Mapper Lithography has introduced its first product, the FLX–1200, which is installed at CEA-Leti in Grenoble (France). This is a mask less lithography system, based on massively parallel electron-beam writing with high-speed optical data transport for switching the electron beams. This FLX platform is initially targeted for 1 wph performance for 28 nm technology nodes, but can also be used for less demanding imaging. The electron source currently integrated is capable of scaling to 10 wph at the same resolution performance, which will be implemented by gradually upgrading the illumination optics. The system has an optical alignment system enabling mix-and-match with optical 193 nm immersion systems using standard NVSM marks. The tool at CEA-Leti is in-line with a Sokudo Duo clean track. Mapper Lithography and CEA-Leti are working in collaboration to develop turnkey solution for specific applications. At previous conferences we have presented imaging results including 28nm node resolution, cross wafer CDu of 2.5nm 3 and a throughput of half a wafer per hour, overhead times included. At this conference we will present results regarding the overlay performance of the FLX-1200. In figure 2 an initial result towards measuring the overlay performance of the FLX-1200 is shown. We have exposed a wafer twice without unloading the wafer in between exposures. In the first exposure half of a dense dot array is exposed. In the second exposure the remainder of the dense dot array is exposed. After development the wafer has been inspected using a CD-SEM at 480 locations distributed over an area of 100mm x 100mm. For each SEM image the shift of the pattern written in the first exposure relative to the pattern written in the second exposure is measured. Cross wafer this shift is 7 nm u+3s in X and 5 nm u+3s in Y. The next step is to evaluate the impact of unloading and loading of the wafer in between exposures. At the conference the latest results will be presented.

Proceedings Article | 10 April 2017 Presentation + Paper

Nanoimprint, DSA, and multi-beam lithography: patterning technologies with new integration challenges

S. Landis, H. Teyssedre, G. Claveau, I. Servin, F. Delachat, M. L. Pourteau, A. Gharbi, P. Pimenta Barros, R. Tiron, L. Nouri, N. Possemé, M. May, P. Brianceau, S. Barnola, Y. Blancquaert, J. Pradelles, P. Essomba, A. Bernadac, B. Dal'zotto, S. Bos, M. Argoud, G. Chamiot-Maitral, A. Sarrazin, C. Tallaron, C. Lapeyre, L. Pain

Proceedings Volume 10149, 101490K (2017) https://doi.org/10.1117/12.2259966

KEYWORDS: Directed self assembly, Lithography, Line width roughness, Nanoimprint lithography, Semiconducting wafers, Etching, Electron beam lithography, System on a chip, Critical dimension metrology, Photoresist processing

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Proceedings Article | 28 March 2017 Paper

Scatterometry control for multiple electron beam lithography

Yoann Blancquaert, Nivea Figueiro, Thibault Labbaye, Francisco Sanchez, Stephane Heraud, Roy Koret, Matthew Sendelbach, Ralf Michel, Shay Wolfling, Stephane Rey, Laurent Pain

Proceedings Volume 10145, 101451F (2017) https://doi.org/10.1117/12.2261389

KEYWORDS: Optical metrology, Electron beam lithography, Scatterometry, Process control, Nanoimprint lithography, Critical dimension metrology, Extreme ultraviolet lithography, Optical lithography, Metrology, Inspection, Scatter measurement, Semiconducting wafers, Error analysis, Maskless lithography, Cadmium sulfide, Nano opto mechanical systems, Lithography

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Proceedings Article | 27 March 2017 Presentation + Paper

A high chi track-compatible DSA for sub-10nm L/S patterning

Douglas Guerrero, Kaumba Sakavuyi, Kui Xu, Ahmed Gharbi, Raluca Tiron, Isabelle Servin, Laurent Pain, Guillaume Claveau, Harold Stokes, Masahiko Harumoto, Célia Nicolet, Xavier Chevalier

Proceedings Volume 10146, 101460W (2017) https://doi.org/10.1117/12.2261094

KEYWORDS: Directed self assembly, Annealing, Optical lithography, Polymers, Scanning electron microscopy, Semiconducting wafers, Silicon, Line width roughness, Glasses, Ultraviolet radiation

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Proceedings Article | 21 March 2017 Paper

Rules-based correction strategies setup on sub-micrometer line and space patterns for 200mm wafer scale SmartNIL process within an integration process flow

H. Teyssedre, S. Landis, P. Brianceau, M. Mayr, C. Thanner, M. Laure, W. Zorbach, M. Eibelhuber, L. Pain, M. Chouiki, M. Wimplinger

Proceedings Volume 10144, 101440V (2017) https://doi.org/10.1117/12.2260002

KEYWORDS: Semiconducting wafers, Nanoimprint lithography, Manufacturing, Critical dimension metrology, Lithography, High volume manufacturing, Calibration, Standards development, Etching, Silicon, Metrology, Scanning electron microscopy

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Proceedings Article | 21 March 2017 Paper

Advanced surface affinity control for DSA contact hole shrink applications

Florian Delachat, Ahmed Gharbi, Patricia Pimenta Barros, Maxime Argoud, Céline Lapeyre, Sandra Bos, Jérôme Hazart, Laurent Pain, Cédric Monget, Xavier Chevalier, Célia Nicolet, Christophe Navarro, Ian Cayrefourcq, Raluca Tiron

Proceedings Volume 10144, 101440O (2017) https://doi.org/10.1117/12.2258043

KEYWORDS: Directed self assembly, Lithography, Immersion lithography, Polymers, Semiconducting wafers, Polymethylmethacrylate, Scanning electron microscopy, Inspection, Image processing, Picosecond phenomena

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Proceedings Article | 20 October 2016 Paper

Critical dimension uniformity characterization of nanoimprinted trenches for high volume manufacturing qualification

H. Teyssedre, S. Landis, C. Thanner, V. Schauer, M. Laure, W. Zorbach, L. Pain, S. Bos, M. Eibelhuber, M. Wimplinger

Proceedings Volume 10032, 100320M (2016) https://doi.org/10.1117/12.2250194

KEYWORDS: High volume manufacturing, Nanoimprint lithography, Semiconducting wafers, Critical dimension metrology, Silicon, Ultraviolet radiation, Polymers, Manufacturing, Metrology, Scanning electron microscopy

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SPIE Journal Paper | 18 October 2016

Process highlights to enhance directed self-assembly contact patterning performances

Ahmed Gharbi, Raluca Tiron, Maxime Argoud, Gaëlle Chamiot-Maitral, Antoine Fouquet, Céline Lapeyre, Patricia Pimenta-Barros, Florian Delachat, Sandra Bos, Shayma Bouanani, Xavier Chevalier, Célia Nicolet, Christophe Navarro, Ian Cayrefourcq, Laurent Pain

JM3, Vol. 15, Issue 04, 043503, (October 2016) https://doi.org/10.1117/12.10.1117/1.JMM.15.4.043503

KEYWORDS: Directed self assembly, Optical lithography, Annealing, Picosecond phenomena, Critical dimension metrology, Scanning electron microscopy, Materials processing, Semiconducting wafers, Lithography, Molecular self-assembly

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Proceedings Article | 19 March 2015 Paper

"Fast" and "thick" e-beam resists exposed with multi-beam tool at 5 keV for implants and mature nodes: experimental and simulated model study

Aurélien Fay, Ndeye Thiam, Marie-Laure Cordini, Isabelle Servin, Christophe Constancias, Ludovic Lattard, Laurent Pain

Proceedings Volume 9423, 94231Q (2015) https://doi.org/10.1117/12.2085832

KEYWORDS: Lithography, Electron beam lithography, Silicon, Point spread functions, Scanning electron microscopy, Critical dimension metrology, 3D modeling, Information technology, Etching, Monte Carlo methods

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Proceedings Article | 8 October 2014 Paper

Assessment of carbon layer growth induced by resists outgassing in multi e-beams lithography

JC Marusic, ML Pourteau, S. Cêtre, L. Pain, AP Mebiene-Engohang, S. David, S. Labau, J. Boussey

Proceedings Volume 9235, 923520 (2014) https://doi.org/10.1117/12.2066152

KEYWORDS: Contamination, Semiconducting wafers, Carbon, Electron beam lithography, Scanning electron microscopy, Lithography, Wafer-level optics, Chemical species, Chemical analysis, Chemically amplified resists

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Proceedings Article | 2 April 2014 Paper

Handling, clamping, and alignment evaluation for multi-beam technology on Matrix1.1 platform

Ludovic Lattard, Jonathan Pradelles, Niels Vergeer, Erwin Slot, Laurent Pain, Erik de Jong, Gianpaolo Torriani, Charles Pieczulewski

Proceedings Volume 9050, 90502E (2014) https://doi.org/10.1117/12.2046233

KEYWORDS: Semiconducting wafers, Optical alignment, Lithography, Sensors, Cooling systems, Electron beam lithography, Interferometers, Manufacturing, Electron beams, Interfaces

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Proceedings Article | 28 March 2014 Paper

Line width roughness reduction strategies for patterns exposed via electron beam lithography

J. Jussot, E. Pargon, B. Icard, J. Bustos, L. Pain

Proceedings Volume 9054, 905405 (2014) https://doi.org/10.1117/12.2047972

KEYWORDS: Line width roughness, Electron beam lithography, Lithography, Plasma, Plasma treatment, Ultraviolet radiation, Gaussian beams, Photoresist materials, Semiconducting wafers, Electron beams

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Proceedings Article | 28 March 2014 Paper

Investigation of the resist outgassing and hydrocarbonaceous contamination induced in multi-electron-beam lithography tools

A.-P. Mebiene-Engohang, M. Pourteau, J. Marusic, L. Pain, T. Nakayama, A. Miyake, M. Smits, S. David, S. Labau, J. Boussey

Proceedings Volume 9049, 90492Q (2014) https://doi.org/10.1117/12.2046350

KEYWORDS: Contamination, Semiconducting wafers, Silicon, Thin film coatings, Scanning electron microscopy, Polymers, Carbon, Projection systems, Chemical species, Lithography

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Proceedings Article | 26 March 2013 Paper

The potential of block copolymer’s directed self-assembly for contact hole shrink and contact multiplication

R. Tiron, A. Gharbi, M. Argoud, X. Chevalier, J. Belledent, P. Pimmenta Barros, I. Servin, C. Navarro, G. Cunge, S. Barnola, L. Pain, M. Asai, C. Pieczulewski

Proceedings Volume 8680, 868012 (2013) https://doi.org/10.1117/12.2011477

KEYWORDS: Etching, Polymethylmethacrylate, Picosecond phenomena, Lithography, Polymers, 193nm lithography, Critical dimension metrology, Oxygen, Neodymium, Directed self assembly

Read Abstract +

Proceedings Article | 26 March 2013 Paper

Matching of beams on the MAPPER MATRIX tool: a simulation study

J. Belledent, G. Z. M. Berglund, P. Brandt, S. Bérard-Bergery, M. Wieland, L. Pain

Proceedings Volume 8680, 86800J (2013) https://doi.org/10.1117/12.2011500

KEYWORDS: Raster graphics, Semiconducting wafers, Critical dimension metrology, Optical simulations, Lithography, Line width roughness, Point spread functions, Electron beams, Error analysis, Electron beam lithography

Read Abstract +

So far, the CMOS technology roadmap has been consistent with Moore’s law, even if manufacturing photolithography tools are now operating beyond their resolution limit. This has been made feasible at the expense of an intensive joint work between designers and process people who have successfully enabled double patterning processes. Tools that can provide photo lithographers with some relief are on their way although not yet in production. Among them, massively parallel mask-less electron beam lithography stands out as a serious candidate since it can achieve the required resolution at the right cost of ownership provided targeted throughput performance is reached. This paper focuses on this latter technique and more precisely, reports on simulation works performed using an emulator of the high volume manufacturing tool being developed by MAPPER Lithography, called MATRIX. In a nutshell, the MATRIX tool will operate using more than 13,000 beams, each one writing a stripe 2μm wide. Each beam itself will be composed of 49 individual sub-beams that can be blanked independently in order to write pixels onto the wafer. The residual placement errors and any current mismatch between the beams will be measured in-situ and corrected through the data path. In order to validate that this concept can actually work, the authors have built an off-line emulator of the data treatment performed down to the information sent to the blanker. It has then been plugged into an electron beam simulator such that the performance on real designs can be tested. In this paper, the methodology used for the corrections is explained as well as the validation process applied. The results of an extensive statistical study are presented showing CD, placement and residual scaling errors simulated on a set of predefined key structures assuming current and misplacement ranges within the MATRIX tool specifications, applying various correction solutions. Based on the collected data, it is shown that CD uniformity on the MATRIX tool is better than +/-10% 3σ taking into account data path, beam variation, stitching and shot noise effects, meeting specifications for circuits designed at 64nm pitch.

Proceedings Article | 23 March 2012 Paper

Comparison of EUV and e-beam lithographic technologies for sub-22-nm node patterning

James Cameron, Jim Thackeray, Jin Wuk Sung, Suzanne Coley, Vipul Jain, Owendi Ongayi, Mike Wagner, Paul LaBeaume, Amy Kwok, David Valeri, Marie Hellion, Béatrice Icard, Bernard Dal'zotto, Claire Sourd, Laurent Pain

Proceedings Volume 8322, 83222F (2012) https://doi.org/10.1117/12.916598

KEYWORDS: Extreme ultraviolet, Electron beam lithography, Extreme ultraviolet lithography, Lithography, Polymers, Semiconductors, Line width roughness, Maskless lithography, Photomasks, EUV optics

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Proceedings Article | 21 March 2012 Paper

Pattern density multiplication by direct self assembly of block copolymers: toward 300mm CMOS requirements

R. Tiron, X. Chevalier, S. Gaugiran, J. Pradelles, H. Fontaine, C. Couderc, L. Pain, C. Navarro, T. Chevolleau, G. Cunge, M. Delalande, G. Fleury, G. Hadziioannou

Proceedings Volume 8323, 83230O (2012) https://doi.org/10.1117/12.916400

KEYWORDS: Lithography, Polymers, 193nm lithography, Electron beam lithography, Silicon, Etching, Photomasks, Picosecond phenomena, Plasma, Directed self assembly

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Proceedings Article | 21 March 2012 Paper

Ultimate lithographic performances of advanced resists CAR or non-CAR resist?

Jan Frederik Van Steenbergen, Noboru Ootsuka, Xavier Buch, Béatrice Icard, Claire Sourd, Christophe Constancias, Bernard Dalzotto, Laurent Pain

Proceedings Volume 8323, 83232M (2012) https://doi.org/10.1117/12.916624

KEYWORDS: Photoresist materials, Lithography, Line width roughness, Electron beam lithography, Extreme ultraviolet, Chemically amplified resists, Electron beams, Semiconducting wafers, Silicon, Chemistry

Read Abstract +

Proceedings Article | 21 March 2012 Paper

Sub-20nm hybrid lithography using optical, pitch-division, and e-beam

J. Belledent, M. Smayling, J. Pradelles, P. Pimenta-Barros, S. Barnola, L. Mage, B. Icard, C. Lapeyre, S. Soulan, L. Pain

Proceedings Volume 8323, 83230F (2012) https://doi.org/10.1117/12.916486

KEYWORDS: Electron beam lithography, Photomasks, Lithography, Optical lithography, Logic, Optics manufacturing, Semiconducting wafers, Double patterning technology, Neodymium, Scanning electron microscopy

Read Abstract +

A roadmap extending far beyond the current 22nm CMOS node has been presented several times. [1] This roadmap includes the use of a highly regular layout style which can be decomposed into "lines and cuts."[2] The "lines" can be done with existing optical immersion lithography and pitch division with self-aligned spacers.[3] The "cuts" can be done with either multiple exposures using immersion lithography, or a hybrid solution using either EUV or direct-write ebeam.[ 4] The choice for "cuts" will be driven by the availability of cost-effective, manufacturing-ready equipment and infrastructure. Optical lithography improvements have enabled scaling far beyond what was expected; for example, soft x-rays (aka EUV) were in the semiconductor roadmap as early as 1994 since optical resolution was not expected for sub-100nm features. However, steady improvements and innovations such as Excimer laser sources and immersion photolithography have allowed some manufacturers to build 22nm CMOS SOCs with single-exposure optical lithography. With the transition from random complex 2D shapes to regular 1D-patterns at 28nm, the "lines and cuts" approach can extend CMOS logic to at least the 7nm node. The spacer double patterning for lines and optical cuts patterning is expected to be used down to the 14nm node. In this study, we extend the scaling to 18nm half-pitch which is approximately the 10-11nm node using spacer pitch division and complementary e-beam lithography. For practical reasons, E-Beam lithography is used as well to expose the "mandrel" patterns that support the spacers. However, in a production mode, it might be cost effective to replace this step by a standard 193nm exposure and applying the spacer technique twice to divide the pitch by 3 or 4. The Metal-1 "cut" pattern is designed for a reasonably complex logic function with ~100k gates of combinatorial logic and flip-flops. Since the final conductor is defined by a Damascene process, the "cut" patterns become islands of resist blocking hard-mask trenches. The shapes are often small and positioned on a dense grid making this layer to be the most critical one. This is why direct-write e-beam patterning, possibly using massively parallel beams, is well suited for this task. In this study, we show that a conventional shaped beam system can already pattern the 11nm node Metal-1 layer with reasonable overlay margin. The combination of design style, optical lithography plus pitch-division, and e-beam lithography appears to provide a scaling path far into the future.

Proceedings Article | 19 May 2011 Paper

193-nm radiation durability study of MoSi binary mask and resulting lithographic performance

Isabelle Servin, Jérôme Belledent, Laurent Pain, Brid Connolly, Martin Sczyrba, Matt Lamantia

Proceedings Volume 8081, 80810X (2011) https://doi.org/10.1117/12.899173

KEYWORDS: Photomasks, Semiconducting wafers, Critical dimension metrology, Scanners, SRAF, Binary data, Lithography, Cadmium, Metrology, Scattering

Read Abstract +

Proceedings Article | 4 April 2011 Paper

EBPC for multi-beams low kV electron projection lithography

Jérôme Belledent, Sébastien Soulan, Laurent Pain

Proceedings Volume 7970, 79701B (2011) https://doi.org/10.1117/12.879424

KEYWORDS: Semiconducting wafers, Point spread functions, Line edge roughness, Calibration, Modulation, Monte Carlo methods, Electron beam lithography, Projection lithography, Printing, Optical proximity correction

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Proceedings Article | 4 April 2011 Paper

IMAGINE: an open consortium to boost maskless lithography take off: first assessment results on MAPPER technology

L. Pain, B. Icard, M. Martin, C. Constancias, S. Tedesco, P. Wiedeman, A. Farah, B. Kampherbeek, C. Pieczulewski, H. Kandrashov

Proceedings Volume 7970, 79700Y (2011) https://doi.org/10.1117/12.881286

KEYWORDS: Lithography, Photoresist processing, Semiconducting wafers, Maskless lithography, Manufacturing, Reliability, Silicon, Electrons, Projection systems, High volume manufacturing

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Proceedings Article | 25 September 2010 Paper

Aging study in advanced photomasks: impact of EFM effects on lithographic performance with MoSi binary and 6% attenuated PSM masks

I. Servin, J. Belledent, M. O. Fialeyre, B. Connolly, M. Lamantia, M. Sczyrba, M. K. Jullian, B. Le Gratiet, L. Pain

Proceedings Volume 7823, 78230N (2010) https://doi.org/10.1117/12.864529

KEYWORDS: Photomasks, Critical dimension metrology, Semiconducting wafers, Reticles, Binary data, Scanning electron microscopy, Scanners, Lithography, Optical proximity correction, Metrology

Read Abstract +

Proceedings Article | 1 April 2010 Paper

Multiple pass exposure in e-beam lithography: application to the sub-22nm nodes

L. Martin, S. Manakli, B. Icard, J. Pradelles, R. Orobtchouk, A. Poncet, L. Pain

Proceedings Volume 7637, 76370E (2010) https://doi.org/10.1117/12.846907

KEYWORDS: Electroluminescence, Modulation, Line edge roughness, Electron beam lithography, Semiconducting wafers, Logic, Metals, Etching, Electron beam direct write lithography, Electron beams

Read Abstract +

Proceedings Article | 23 September 2009 Paper

Predictive modeling for EBPC in EBDW

Rainer Zimmermann, Martin Schulz, Wolfgang Hoppe, Hans-Jürgen Stock, Wolfgang Demmerle, Alex Zepka, Artak Isoyan, Lars Bomholt, Serdar Manakli, Laurent Pain

Proceedings Volume 7488, 74883J (2009) https://doi.org/10.1117/12.833482

KEYWORDS: Data modeling, 3D modeling, Electron beam direct write lithography, Point spread functions, Critical dimension metrology, Model-based design, Geometrical optics, Cadmium, Error analysis, Virtual reality

Read Abstract +

Proceedings Article | 23 September 2009 Paper

Development of multiple pass exposure in electron beam direct write lithography for sub-32nm nodes

L. Martin, S. Manakli, B. Icard, J. Pradelles, R. Orobtchouk, A. Poncet, L. Pain

Proceedings Volume 7488, 74881C (2009) https://doi.org/10.1117/12.829893

KEYWORDS: Electroluminescence, Electron beam direct write lithography, Standards development, Electron beam lithography, Optical lithography, Semiconducting wafers, Electron beams, Lithography, Line edge roughness, Optics manufacturing

Read Abstract +

Proceedings Article | 27 May 2009 Paper

High resolution cell projection

U. Weidenmueller, P. Hahmann, M. Lemke, B. Schnabel, L. Pain, S. Manakli

Proceedings Volume 7470, 74700P (2009) https://doi.org/10.1117/12.835187

KEYWORDS: Vestigial sideband modulation, Electron beam direct write lithography, Electron beam lithography, Beam shaping, Scanning electron microscopy, Standards development, Lithography, Prototyping, Semiconducting wafers, Electron beams

Read Abstract +

The ever more demanding requirements in the semiconductor manufacturing sector together with the increasing mask making costs and cycle times call for new lithographic solutions. Electron beam lithography has shown its superior performance and flexibility in advanced patterning applications. It enables already today process and technology developments ahead of the ITRS roadmap, which addresses currently the 32nm and 22nm node or even below. Thus electron beam direct write (EBDW) can avoid the high costs and delay times related to the advanced masks required for critical layers. On the other side EBDW faces the concerns regarding its throughput, which bases upon the inherited sequential exposure method. A solution to improve the throughput performance offers the implementation of the cell projection method as already materialized in the Vistec SB3055 tool. In addition to the variable shape beam technology, which can project regular structures (rectangles, slants and triangles) only, cell projection is able to image complex structures. Thus, structures that would have required a multiple of regular shots are now projected in one single shot. Thanks to this approach not only the shot count is noticeably reduced, but also the overall throughput is increased. First experimental and simulation results show an improvement of a factor of about 3X. Nevertheless, the final throughput gain strongly depends on the pattern and data structure itself. Combining high resolution variable shape beam technology with the cell projection feature allows advanced R&D and small volume and prototyping applications to be performed with one system. The Vistec SB3055 features the high resolution capability of variable shape beam lithography and incorporates the advantages of the cell projection technology. Owing to this new option we are able to improve the throughput for standard design features while maintaining the required high accuracy of our exposure system. Beside this, the combination of cell projection and standard shape beam technology still offers a high degree of flexibility as the key advantage of EBDW. On the Vistec SB3055 system we have performed different resolution tests serving as comparison between cell projection and standard shape beam. In this paper we will present the resolution capability obtained with cell projection on test structures as well as the general accuracy achieved for real patterns.

Proceedings Article | 27 May 2009 Paper

New writing strategy in electron beam direct write lithography to improve critical dense lines patterning for sub-45nm nodes

L. Martin, S. Manakli, B. Icard, J. Pradelles, R. Orobtchouk, A. Poncet, L. Pain

Proceedings Volume 7470, 74700R (2009) https://doi.org/10.1117/12.835189

KEYWORDS: Electroluminescence, Line edge roughness, Electron beam lithography, Electron beam direct write lithography, Modulation, Scattering, Optical lithography, Point spread functions, Standards development, Lithography

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Proceedings Article | 20 March 2009 Paper

Cell projection use in maskless lithography for 45nm and 32nm logic nodes

S. Manakli, H. Komami, M. Takizawa, T. Mitsuhashi, L. Pain

Proceedings Volume 7271, 72710K (2009) https://doi.org/10.1117/12.814730

KEYWORDS: Vestigial sideband modulation, Electron beam lithography, Beam shaping, Lithography, Electron beams, Logic, Semiconducting wafers, Optical lithography, Software development, Projection lithography

Read Abstract +

Proceedings Article | 18 March 2009 Paper

Development of resist process for 5-KV multi-beam technology

B. Icard, D. Rio, P. Veltman, B. Kampherbeek, C. Constancias, L. Pain

Proceedings Volume 7271, 72710R (2009) https://doi.org/10.1117/12.813687

KEYWORDS: Photoresist processing, Semiconducting wafers, Polymethylmethacrylate, Electron beam lithography, Electrons, Line edge roughness, Lithography, Standards development, Semiconductors, Manufacturing

Read Abstract +

Proceedings Article | 2 May 2008 Paper

New alignment marks for improved measurement maturity

U. Weidenmueller, H. Alves, B. Schnabel, B. Icard, L. Pain, J.-C. Le Denmat, S. Manakli, J. Pradelles

Proceedings Volume 6792, 679211 (2008) https://doi.org/10.1117/12.798788

KEYWORDS: Optical alignment, Semiconducting wafers, Optical lithography, Electron beams, Electron beam direct write lithography, Lithography, Signal to noise ratio, Overlay metrology, Signal detection, Wafer testing

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Proceedings Article | 28 March 2008 Paper

High throughput maskless lithography: low voltage versus high voltage

S. W. H. Steenbrink, B. Kampherbeek, M. Wieland, J. Chen, S. Chang, M. Pas, J. Kretz, C. Hohle, D. van Steenwinckel, S. Manakli, J. Le-Denmat, L. Pain

Proceedings Volume 6921, 69211T (2008) https://doi.org/10.1117/12.771971

KEYWORDS: Semiconducting wafers, Scattering, Silicon, Critical dimension metrology, Electron beam lithography, Laser scattering, Lenses, Lithography, Modulation transfer functions, Maskless lithography

Read Abstract +

Proceedings Article | 28 March 2008 Paper

MAGIC: a European program to push the insertion of maskless lithography

L. Pain, B. Icard, S. Tedesco, B. Kampherbeek, G. Gross, C. Klein, H. Loeschner, E. Platzgummer, R. Morgan, S. Manakli, J. Kretz, C. Holhe, K.-H. Choi, F. Thrum, E. Kassel, W. Pilz, K. Keil, J. Butschke, M. Irmscher, F. Letzkus, P. Hudek, A. Paraskevopoulos, P. Ramm, J. Weber

Proceedings Volume 6921, 69211S (2008) https://doi.org/10.1117/12.772472

KEYWORDS: Semiconducting wafers, Lithography, Photomasks, Manufacturing, Electron beams, Electron beam lithography, Nanofabrication, Computed tomography, Prototyping, Maskless lithography

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SPIE Journal Paper | 1 July 2007

Complementary dose and geometrical solutions for electron beam direct write lithography proximity effects correction: application for sub-45-nm node product manufacturing

Serdar Manakli, C. Soonekindt, Laurent Pain, J. Le Denmat, Jerome Todeschini, B. Icard, B. Minghetti

JM3, Vol. 6, Issue 03, 033001, (July 2007) https://doi.org/10.1117/12.10.1117/1.2770472

KEYWORDS: Modulation, Critical dimension metrology, Electron beam direct write lithography, Point spread functions, Electron beam lithography, Cadmium sulfide, Electron beams, Optical lithography, Manufacturing, Backscatter

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Proceedings Article | 3 May 2007 Paper

Electron beam direct write: shaped beam overcomes resolution concerns

Ines Stolberg, Laurent Pain, Johannes Kretz, Monika Boettcher, Hans-Joachim Doering, Juergen Gramss, Peter Hahmann

Proceedings Volume 6533, 65330J (2007) https://doi.org/10.1117/12.736974

KEYWORDS: Electron beam direct write lithography, Electron beams, Vestigial sideband modulation, Semiconductors, Prototyping, Manufacturing, Photomasks, Beam shaping, Electron beam lithography, Lithography

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Proceedings Article | 3 May 2007 Paper

Electron beam lithography simulation based on a single convolution approach: application for sub-45nm nodes

J. Le denmat, S. Manakli, B. Icard, C. Soonekindt, B. Minghetti, O. Le borgne, L. Pain

Proceedings Volume 6533, 653319 (2007) https://doi.org/10.1117/12.736519

KEYWORDS: Monte Carlo methods, Point spread functions, Electron beam direct write lithography, Optical simulations, Electron beam lithography, Electron beams, Convolution, Scattering, Photoresist processing, Laser scattering

Read Abstract +

Proceedings Article | 6 May 2005 Paper

Electron beam direct write lithography flexibility for ASIC manufacturing: an opportunity for cost reduction

L. Pain, M. Jurdit, J. Todeschini, S. Manakli, B. Icard, B. Minghetti, G. Bervin, A. Beverina, F. Leverd, M. Broekaart, P. Gouraud, V. De Jonghe, Ph. Brun, S. Denorme, F. Boeuf, V. Wang, D. Henry

Proceedings Volume 5751, (2005) https://doi.org/10.1117/12.601498

KEYWORDS: Photomasks, Electron beam direct write lithography, Manufacturing, Lithography, Optical proximity correction, Semiconducting wafers, Optics manufacturing, Optical lithography, Standards development, Photoresist processing

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Proceedings Article | 4 May 2005 Paper

Electron beam direct write process development for sub 45nm CMOS manufacturing

J. Todeschini, Laurent Pain, S. Manakli, B. Icard, V. DeJonghe, B. Minghetti, M. Jurdit, D. Henry, V. Wang

Proceedings Volume 5753, (2005) https://doi.org/10.1117/12.601616

KEYWORDS: Line width roughness, Electron beam direct write lithography, Semiconducting wafers, Electron beam lithography, Electron beams, Manufacturing, Etching, Photoresist processing, Coating, Semiconductors

Read Abstract +

Proceedings Article | 20 May 2004 Paper

Manufacturing concerns for advanced CMOS circuit realization EBDW alternative solution for cost and cycle time reductions

Laurent Pain, M. Jurdit, Yves LaPlanche, J. Todeschini, Serdar Manakli, G. Bervin, Ramiro Palla, A. Beverina, R. Faure, X. Bossy, H. Leininger, S. Tourniol, M. Broekaart, F. Judong, K. Brosselin, P. Gouraud, Veronique De Jonghe, Daniel Henry, M. Woo, Peter Stolk, B. Tavel, F. Arnaud

Proceedings Volume 5374, (2004) https://doi.org/10.1117/12.537188

KEYWORDS: Electron beam direct write lithography, Manufacturing, Semiconducting wafers, Lithography, Optical alignment, Control systems, Electron beam lithography, Photomasks, Photoresist processing, Optics manufacturing

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Proceedings Article | 16 June 2003 Paper

Advanced patterning studies using shaped e-beam lithography for 65-nm CMOS preproduction

Laurent Pain, Murielle Charpin, Yves Laplanche, David Herisson, J. Todeschini, Ramiro Palla, A. Beverina, H. Leininger, S. Tourniol, M. Broekaart, Emmanuelle Luce, F. Judong, K. Brosselin, Y. Le Friec, F. Leverd, S. Del Medico, V. De Jonghe, Daniel Henry, M. Woo, F. Arnaud

Proceedings Volume 5037, (2003) https://doi.org/10.1117/12.482336

KEYWORDS: Etching, Electron beam lithography, Lithography, Semiconducting wafers, Optical alignment, Photomasks, Chemistry, Scanners, Oxides, CMOS technology

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Proceedings Article | 16 June 2003 Paper

Mix and match capability of e-beam direct-write for the 65-nm technology

Yves Laplanche, Murielle Charpin, Laurent Pain, J. Todeschini, Daniel Henry, Pierre-Olivier Sassoulas, S. Gough, Ulf Weidenmueller, Peter Hahmann

Proceedings Volume 5037, (2003) https://doi.org/10.1117/12.482342

KEYWORDS: Semiconducting wafers, Scanners, Optical alignment, Electron beam direct write lithography, Distortion, Overlay metrology, Electron beam lithography, Photomasks, Optical lithography, Error analysis

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Proceedings Article | 24 July 2002 Paper

Negative-tone CAR resists for e-beam lithography: modification of chemical composition for R&D application (high resolution) or production application (high sensitivity)

Murielle Charpin, Laurent Pain, Serge Tedesco, C. Gourgon, A. Andrei, Daniel Henry, Yves LaPlanche, Ryotaro Hanawa, Tadashi Kusumoto, Masumi Suetsugu, H. Yokoyama

Proceedings Volume 4690, (2002) https://doi.org/10.1117/12.474193

KEYWORDS: Polymers, Electron beam lithography, Etching, Lithography, Palladium, Industrial chemicals, Semiconducting wafers, Diffusion, Prototyping, Critical dimension metrology

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Proceedings Article | 1 July 2002 Paper

Shaped e-beam lithography integration work for advanced ASIC manufacturing: progress report

Laurent Pain, Murielle Charpin, Yves LaPlanche, Daniel Henry

Proceedings Volume 4688, (2002) https://doi.org/10.1117/12.472335

KEYWORDS: Semiconducting wafers, Photomasks, Photoresist processing, Standards development, Etching, Lithography, Electron beam lithography, Manufacturing, Optical lithography, Prototyping

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Proceedings Article | 24 August 2001 Paper

Resist composition effects on ultimate resolution of negative-tone chemically amplified resists

Laurent Pain, C. Gourgon, K. Patterson, B. Scarfogliere, Serge Tedesco, Gilles Fanget, B. Dal'zotto, M. Ribeiro, Tadashi Kusumoto, Masumi Suetsugu, Ryotaro Hanawa

Proceedings Volume 4345, (2001) https://doi.org/10.1117/12.436854

KEYWORDS: Polymers, Etching, Lithography, Diffusion, FT-IR spectroscopy, Photoresist processing, Deep ultraviolet, Chemically amplified resists, Optical lithography, Statistical analysis

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Proceedings Article | 24 August 2001 Paper

Modification of 193-nm (ArF) photoresists by electron beam stabilization

Patrick Martens, Shigeki Yamamoto, Kunishige Edamatsu, Yasunori Uetani, Laurent Pain, Ramiro Palla, Matthew Ross, William Livesay

Proceedings Volume 4345, (2001) https://doi.org/10.1117/12.436842

KEYWORDS: Etching, Electron beams, Photoresist processing, Lithography, 193nm lithography, Refraction, FT-IR spectroscopy, Scanning electron microscopy, Photoresist materials, Critical dimension metrology

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For the sub 130nm technology nodes, 193nm(ArF) lithography has become the technology path of choice. Similar to the 248nm technology set, the resist systems being used for 193nm lithography are based on chemical amplification to achieve high throughput at the low exposure energy at 193nm. The current ArF resist systems have experienced problems with etch selectivity and line slimming during CD-SEM measurement. Both of these issues are related to the resist platform and constituents used to achieve the desired lithographic performance. This investigation evaluates electron beam stabilization as a way of addressing both the etch selectivity and line slimming issues associated with some of the current 193nm resist systems. Varying levels of electron beam dose were evaluated in an attempt to understand the effects of energetic electrons on ArF resist materials. Chemical changes in the resist were monitored for blanket resist films by FTIR, film shrinkage, and changes in index of refraction, all as a function of dose level. An increase in modification of the resist is seen with increasing dose. Blanket resist etch rate studies were performed as a function of stabilization condition. The etch rate of the resist was found to decrease with increasing dose as compared to untreated resist. Correlation of the chemical changes and etch rate reductions are proposed for the resists considered. The CD changes induced by the electron beam stabilization were monitored as a function of dose applied. Minimal CD change was seen as a result of the stabilization process. The impact of the electron beam process on line slimming was evaluated by performing repeated measurements on resist features with different levels of electron beam dose. The line slimming was found to be significantly reduced for the higher dose levels considered. Etch selectivity was evaluated by cross-section SEM measurements after etch of features with different levels of stabilization. An increase in the etch selectivity and pattern stability were observed with increasing stabilization dose.

Proceedings Article | 22 August 2001 Paper

193-nm metrology: facing severe e-beam/resist interaction phenomena

Mauro Vasconi, Maddalena Bollin, Gina Cotti, Laurent Pain, Vincent Tirard

Proceedings Volume 4344, (2001) https://doi.org/10.1117/12.436791

KEYWORDS: Critical dimension metrology, Scanning electron microscopy, Semiconducting wafers, Photoresist materials, Metrology, Electron beams, Target detection, Photoresist processing, Silicon, Ultraviolet radiation

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Proceedings Article | 23 June 2000 Paper

Bake condition effect on hybrid lithography process for negative-tone chemically amplified resists

Laurent Pain, F. Sala, C. Higgins, B. Dal'zotto, Serge Tedesco

Proceedings Volume 3999, (2000) https://doi.org/10.1117/12.388357

KEYWORDS: Lithography, Critical dimension metrology, Deep ultraviolet, Diffusion, Chemically amplified resists, Electron beam lithography, Photoresist processing, Temperature metrology, Scanning electron microscopy, Chlorine

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Proceedings Article | 2 June 2000 Paper

193-nm scanner characterization by SEM and electrical CD measurements

Laurent Pain, Yorick Trouiller, Alexandra Barberet, O. Guirimand, Gilles Fanget, N. Martin, Yves Quere, M. Nier, Emile Lajoinie, Didier Louis, Michel Heitzmann, P. Scheiblin, A. Toffoli

Proceedings Volume 3998, (2000) https://doi.org/10.1117/12.386499

KEYWORDS: Scanning electron microscopy, Resistance, Etching, Lithography, Scanners, Calibration, Chemistry, Oxides, Critical dimension metrology, Photomasks

Read Abstract +

Proceedings Article | 14 June 1996 Paper

Free volume variations during exposure and PEB of DUV positive resists: effect on dissolution properties

Laurent Pain, Charles Le Cornec, Charles Rosilio, Patrick Paniez

Proceedings Volume 2724, (1996) https://doi.org/10.1117/12.241878

KEYWORDS: Polymers, Deep ultraviolet, Lithography, Polymer thin films, Temperature metrology, Chemical reactions, Diffusion, Molecules, Chemistry, Photoresist processing

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Proceedings Article | 9 June 1995 Paper

Optimization of CD control in DUV positive resists: influence of photoresist viscoelastic properties on PEB conditions

Francoise Vinet, N. Buffet, Pierre Fanton, Laurent Pain, Patrick Paniez

Proceedings Volume 2438, (1995) https://doi.org/10.1117/12.210408

KEYWORDS: Diffusion, Deep ultraviolet, Temperature metrology, Critical dimension metrology, Lithography, Polymers, Surface conduction electron emitter displays, Photoresist materials, Process control, Scanning electron microscopy

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