When compressing massive data, using software implementation of Zstandard (Zstd) algorithm will occupy a lot of processor resources, and it will lead to performance bottleneck due to serial data dependency, hardware acceleration of Zstd algorithm is an effective solution to the above problems. Therefore, in this paper, we propose a hardware architecture for concurrent streaming of multiple hash tables applicable to the Zstd algorithm. Using this design scheme, the RTL-based VCS simulation verification shows that the compression ratio almost reaches the standard of software, the compression speed of hardware is about 5.5 times of software compression speed, and the decompression speed of hardware is about 5 times of software, where the compression speed reaches up to 1.17GB/s and decompression speed reaches up to 1.89GB/s, and compared with the existing hardware implementation of Zstd, the compression speed is about 11.4% higher than that of the existing hardware implementation of Zstd.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.