Process Window Qualification (PWQ) is a well-known wafer inspection technique used to qualify the IC manufacturing lithography process window. Circuit designs are becoming denser and more complex in advanced semiconductor process technologies. Therefore, yield is becoming increasingly sensitive to defects. How to detect wafer defects at an early stage is the key to improving wafer yield. Additionally, shortening the PWQ total turn around run time is an important factor for a wafer yield improvement methodology. In this paper, the Winbond OPC team and Cadence Pegasus DFM team initiated a project to improve the PWQ run time and accuracy using a pattern analysis flow. This flow includes defect data pre-processing, classification, and filtering, including the use of CD-SEM image auto-alignment to improve extraction locations and wafer results. The huge data volumes are reduced in order to create easy to review results. This flow reduces the PWQ processing time and correctly finds real wafer defects to improve process windows and yield.
Optical Proximity Correction (OPC) is an important step in the optical lithography-based manufacturing process. Starting from 115 nm, lithography processes typically use OPC to resolve features acceptably. Advanced OPC technologies use model-based edge segment adjustments to achieve highly accurate corrections. The typical process for optical proximity correction suffers from a huge turn-around-time (TAT) and is well known to have time-consuming complexity especially at 40 nm and below. Therefore, in order to speed up process development and increase qualified pattern variations with good yield, we must find ways to speed up the OPC TAT. This paper presents a flow to construct layout hierarchy and increase OPC cell/template re-use to greatly reduce the OPC TAT using the Pegasus Computational Pattern Analytics (CPA) software.
A multi-objective optimization flow is developed to identify balanced compact optical proximity correction (OPC) models with ideal calibration accuracy, runtime performance and prediction accuracy. We demonstrate a model selection process based on Pareto front optimization to meet multiple modeling requirements in a single optimization step. A genetic search algorithm determines the final population that offers the best trade-off in set model properties. As a demonstration, we cooptimize calibration accuracy, verification accuracy and term count in a mode developed for hot spot prediction for a line and space memory layer. The optimization determines the minimum number of model terms to meet the off-nominal dose and focus patterning accuracy requirements in verification. Multi-objective optimization provides better verification process window condition (PWC) accuracy because of the multi-objective trade-off built into the genetic algorithm (GA). The optimizer also provides better calibration accuracy (Rms Weighted) than compact models with a fixed configuration because model composition is optimized during GA search. The resulting champion model is 30% more predictive and 5% faster in simulation using this approach. Results for a negative tone develop hole layer with a model complexity of up to 44 terms are also analyzed based on nominal only measurement data. We further show the models selected by multi-objective optimization have a lesser tendency to over-fit the calibration data. The methodology can be applied to streamline complex models for optimum performance and target error rate. In many cases, for smaller data sets, we show that simplified models provide improved verification accuracy within metrology error limits.
Beyond the 40nm technology node, layout weak points and hotspot types increase dramatically. Many hotspots can be detected by OPC simulation. However, in advanced nodes, OPC simulation suffers from a long turn-around-time (TAT) and is challenged to handle the additional design complexity. Therefore, in order to speed up the process and OPC development, an efficient OPC hotspot detection method is required. This paper presents a flow using Pegasus Computational Pattern Analytics (CPA) technology from Cadence to extract a comprehensive set of patterns to build a pattern bank from a layout source. We can then compare two or more different banks (diffing) to find new patterns which have not been processed before. OPC engineers can analyze these new patterns to check for any OPC issues instead of simulating a full chip. This flow provides a much higher efficiency and better performance while allowing the storage of pattern banks over time to build history and yield experience. Over time, each new layout introduced for OPC can be processed faster because more patterns have been added to the banks and less simulation time is needed.
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