Mr. Ludovic Lattard Profile

Ludovic Lattard

Senior Manager at Formfactor

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Publications (9)

Proceedings Article | 27 April 2017 Presentation

Overlay performance assessment of MAPPER's FLX-1200 (Conference Presentation)

Ludovic Lattard, Isabelle Servin, Jonathan Pradelles, Yoann Blancquaert, Guido Rademaker, Laurent Pain, Guido de Boer, Pieter Brandt, Michel Dansberg, Remco J. Jager, Jerry J. Peijster, Erwin Slot, Stijn W. H. Steenbrink, Niels Vergeer, Marco Wieland

Proceedings Volume 10144, 101440N (2017) https://doi.org/10.1117/12.2260878

KEYWORDS: Semiconducting wafers, Lithography, Electron beam lithography, Photomasks, Switching, Electron beams, Lithographic illumination, Integrated optics, Optical alignment, Wafer-level optics

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Mapper Lithography has introduced its first product, the FLX–1200, which is installed at CEA-Leti in Grenoble (France). This is a mask less lithography system, based on massively parallel electron-beam writing with high-speed optical data transport for switching the electron beams. This FLX platform is initially targeted for 1 wph performance for 28 nm technology nodes, but can also be used for less demanding imaging. The electron source currently integrated is capable of scaling to 10 wph at the same resolution performance, which will be implemented by gradually upgrading the illumination optics. The system has an optical alignment system enabling mix-and-match with optical 193 nm immersion systems using standard NVSM marks. The tool at CEA-Leti is in-line with a Sokudo Duo clean track. Mapper Lithography and CEA-Leti are working in collaboration to develop turnkey solution for specific applications. At previous conferences we have presented imaging results including 28nm node resolution, cross wafer CDu of 2.5nm 3 and a throughput of half a wafer per hour, overhead times included. At this conference we will present results regarding the overlay performance of the FLX-1200. In figure 2 an initial result towards measuring the overlay performance of the FLX-1200 is shown. We have exposed a wafer twice without unloading the wafer in between exposures. In the first exposure half of a dense dot array is exposed. In the second exposure the remainder of the dense dot array is exposed. After development the wafer has been inspected using a CD-SEM at 480 locations distributed over an area of 100mm x 100mm. For each SEM image the shift of the pattern written in the first exposure relative to the pattern written in the second exposure is measured. Cross wafer this shift is 7 nm u+3s in X and 5 nm u+3s in Y. The next step is to evaluate the impact of unloading and loading of the wafer in between exposures. At the conference the latest results will be presented.

Proceedings Article | 22 March 2016 Paper

Complete data preparation flow for Massively Parallel E-Beam lithography on 28nm node full-field design

Aurélien Fay, Clyde Browning, Pieter Brandt, Jacky Chartoire, Sébastien Bérard-Bergery, Jérôme Hazart, Alexandre Chagoya, Sergei Postnikov, Mohamed Saib, Ludovic Lattard, Patrick Schavione

Proceedings Volume 9777, 977714 (2016) https://doi.org/10.1117/12.2219178

KEYWORDS: Electron beam lithography, Lithography, Optical lithography, Photoresist processing, Software development, Semiconducting wafers, Optical simulations, Electronic design automation, Data modeling, Metrology, Point spread functions, Electroluminescence, Logic, Critical dimension metrology, Calibration, Manufacturing

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Massively parallel mask-less electron beam lithography (MP-EBL) offers a large intrinsic flexibility at a low cost of ownership in comparison to conventional optical lithography tools. This attractive direct-write technique needs a dedicated data preparation flow to correct both electronic and resist processes. Moreover, Data Prep has to be completed in a short enough time to preserve the flexibility advantage of MP-EBL. While the MP-EBL tools have currently entered an advanced stage of development, this paper will focus on the data preparation side of the work for specifically the MAPPER Lithography FLX-1200 tool [1]-[4], using the ASELTA Nanographics Inscale software. The complete flow as well as the methodology used to achieve a full-field layout data preparation, within an acceptable cycle time, will be presented. Layout used for Data Prep evaluation was one of a 28 nm technology node Metal1 chip with a field size of 26x33mm², compatible with typical stepper/scanner field sizes and wafer stepping plans. Proximity Effect Correction (PEC) was applied to the entire field, which was then exported as a single file to MAPPER Lithography’s machine format, containing fractured shapes and dose assignments. The Soft Edge beam to beam stitching method was employed in the specific overlap regions defined by the machine format as well. In addition to PEC, verification of the correction was included as part of the overall data preparation cycle time. This verification step was executed on the machine file format to ensure pattern fidelity and accuracy as late in the flow as possible. Verification over the full chip, involving billions of evaluation points, is performed both at nominal conditions and at Process Window corners in order to ensure proper exposure and process latitude. The complete MP-EBL data preparation flow was demonstrated for a 28 nm node Metal1 layout in 37 hours. The final verification step shows that the Edge Placement Error (EPE) is kept below 2.25 nm over an exposure dose variation of 8%.

Proceedings Article | 22 March 2016 Paper

Non-CAR resists and advanced materials for Massively Parallel E-Beam Direct Write process integration

Marie-Line Pourteau, Isabelle Servin, Kévin Lepinay, Cyrille Essomba, Bernard Dal'Zotto, Jonathan Pradelles, Ludovic Lattard, Pieter Brandt, Marco Wieland

Proceedings Volume 9777, 977713 (2016) https://doi.org/10.1117/12.2218884

KEYWORDS: Line width roughness, Lithography, Electron beam lithography, Electron beams, Scanning electron microscopy, Etching, Semiconducting wafers, Neodymium, Silicon, Surface conduction electron emitter displays

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Proceedings Article | 19 March 2015 Paper

Ready for multi-beam exposure at 5kV on MAPPER tool: lithographic and process integration performances of advanced resists/stack

Isabelle Servin, Ndeye Arame Thiam, Patricia Pimenta-Barros, Marie-Line Pourteau, Armel-Petit Mebiene, Julien Jussot, Jonathan Pradelles, Philippe Essomba, Ludovic Lattard, Pieter Brandt, Marco Wieland

Proceedings Volume 9423, 94231C (2015) https://doi.org/10.1117/12.2085915

KEYWORDS: Line width roughness, Lithography, Etching, Electron beam lithography, System on a chip, Metals, Scanning electron microscopy, Silicon, Resistance, Extreme ultraviolet

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Proceedings Article | 19 March 2015 Paper

"Fast" and "thick" e-beam resists exposed with multi-beam tool at 5 keV for implants and mature nodes: experimental and simulated model study

Aurélien Fay, Ndeye Thiam, Marie-Laure Cordini, Isabelle Servin, Christophe Constancias, Ludovic Lattard, Laurent Pain

Proceedings Volume 9423, 94231Q (2015) https://doi.org/10.1117/12.2085832

KEYWORDS: Lithography, Electron beam lithography, Silicon, Point spread functions, Scanning electron microscopy, Critical dimension metrology, 3D modeling, Information technology, Etching, Monte Carlo methods

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Proceedings Article | 2 April 2014 Paper

Handling, clamping, and alignment evaluation for multi-beam technology on Matrix1.1 platform

Ludovic Lattard, Jonathan Pradelles, Niels Vergeer, Erwin Slot, Laurent Pain, Erik de Jong, Gianpaolo Torriani, Charles Pieczulewski

Proceedings Volume 9050, 90502E (2014) https://doi.org/10.1117/12.2046233

KEYWORDS: Semiconducting wafers, Optical alignment, Lithography, Sensors, Cooling systems, Electron beam lithography, Interferometers, Manufacturing, Electron beams, Interfaces

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Proceedings Article | 26 March 2013 Paper

MAPPER alignment sensor evaluation on process wafers

N. Vergeer, L. Lattard, G. de Boer, F. Couweleers, D. Dave, J. Pradelles, J. Bustos

Proceedings Volume 8680, 86801E (2013) https://doi.org/10.1117/12.2011402

KEYWORDS: Optical alignment, Semiconducting wafers, Sensors, Reflectivity, Reflection, System on a chip, Lithography, Wafer-level optics, Silicon, Maskless lithography

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Proceedings Article | 13 March 2012 Paper

Spacer process and alignment assessment for SADP process

L. Lattard, M. McCallum, R. Morton, T. Fujiwara, K. Makino, A. Tokui, N. Takahashi, S. Sasamoto

Proceedings Volume 8326, 832604 (2012) https://doi.org/10.1117/12.916362

KEYWORDS: Optical alignment, System on a chip, Lithography, Semiconducting wafers, Image processing, Optical lithography, Scanning electron microscopy, Scanners, Signal processing, Photoresist processing

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Proceedings Article | 23 March 2011 Paper

Scanner alignment performance for double patterning

L. Lattard, M. McCallum, R. Morton, C. Lapeyre, K. Makino, A. Tokui, N. Takahashi, T. Fujiwara

Proceedings Volume 7973, 79730I (2011) https://doi.org/10.1117/12.878953

KEYWORDS: Optical alignment, Double patterning technology, Scanners, Lithography, Overlay metrology, Optical lithography, Critical dimension metrology, Semiconducting wafers, Double positive medium, Etching

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