KEYWORDS: Overlay metrology, Semiconducting wafers, Logic devices, Error analysis, Lithography, Logic, Control systems, Optical alignment, Metrology, Front end of line
To satisfy the tight budget of critical dimension, an immersion exposure process is widely applied to critical layers
of the recent advanced devices to accomplish the high performance of resolution. In our 40nm node logic devices,
the overlay accuracy of the critical layers (immersion to immersion) would be required to be less than 15nm
(Mean+3sigma) and the one of the sub-critical layers (dry to immersion) would be required to be less than 20nm
(Mean+3sigma). Furthermore, the overlay accuracy of the critical layers might be less than 10nm (Mean+3sigma) in
the 32nm node logic devices. The method of improving the overlay performance should be investigated for mass
production in the future.
In this report, attaching weight to productivity, we selected the technique of high order process correction with
machine configuration and applied it for 40 nm node production. We evaluated the overlay performance of the
critical layers using 40nm process stack wafer and found that high order grid compensation was effective for
reducing the process impact on the overlay accuracy. Furthermore, about the sub-critical layers, high order grid
compensation was also effective for controlling the tool matching error.
65-55nm Logic-Devices require high performance of not only the resolution, of but also the overlay accuracy
(Mean+3sigmas < 20-30nm). Thus, here, overlay performance of several layers in our advanced devices is investigated
with using Immersion-exposure-tool. We used the new alignment system called SMASHTM which has the phase grating
alignment sensor newly installed in our immersion-exposure-tool (XT1400Ei). SMASH supports flexible mark design in
terms of size and pitch of the grating so that it can comply for our design requirement. SMASH has much smaller
alignment beam size of ~ 40um for it.
New mark design for our 65-55nm process will be investigated so as to obtain higher alignment accuracy than that of
current marks. The alignment performance becomes more accurate proportionally to data density of the mark and it
depends on the diffraction angle and efficiency from the mark. Thus, to obtain acceptable alignment accuracy with
smaller mark, it should be designed such as diffraction efficiency is maximized within the required boundary condition
in the pitch [diffraction angle] and segmentation of the mark.
In this paper, several new marks are designed and evaluated. The evaluation shows that comparable performance could
be obtained in the new design mark as in ASML's conventional marks. Finally, we select one from the new smaller
marks and apply it to our 65-55nm process, especially, to the five process modules (Gate-to-Active, Contact-to-Gate,
Metal1-to-Contact, Via1-to-Metal1, Metal2-to-Via1), and performance within 20nm (Mean+3sigmas) are typically
obtained. The overlay accuracy needed for our 65-55nm Logic-Devices is successfully achieved with
immersion-exposure-tool.
SMASH* (SMart Alignment Sensor Hybrid): the name of alignment system using with phase grating alignment sensor.
Electron beam (EB) lithography has often been used for fabricating advanced ULSIs. Recently, to increase the writing throughput, electron beam projection lithography (EBPL) technology has been proposed (100kV acceleration voltage and 20-30(mu) A total currents). When we introduce the EBPL to practical use, it is important to develop a projection mask and a mask data conversion system, because there are many differences between the EBPL mask data and the conventional EB data. In EBPL mask conversion system, it is necessary to divide a full chip data into several 1mm X 1mm (250micrometers X 250micrometers on the wafer) sub-fields, which size is as same as one EBPL shot with format conversion. In this paper, we show the data conversion system that converts pattern data (GDS+U) to EBPL mask data. This system can maintain the hierarchy data structure in the dividing process. The patterns that located on the boundary between neighboring fields were treated as belonging in either field for preventing critical division. As a result, a data conversion system for EBPL mask, that can divide the device data with high speed and high quality, was successfully obtained.
KEYWORDS: Quantum efficiency, Projection lithography, Lithography, Electron beam direct write lithography, Electron beam lithography, Electron beams, Photomasks, Scanning electron microscopy, Molecules, Chemical analysis
Electron beam (EB) lithography has often been used for fabricating advanced ULSIs. Recently, to increase the throughput, EB projection lithography (EPL) has been proposed. If 100 kV acceleration voltage and 20 to 30 (mu) A beam current are to be adopted in this technology, a high sensitivity resist will have to be developed to achieve a throughput of more than 30 wafers/hour (8'(phi) ). In this paper, we show the photoacid generator (PAG) optimization of a polyhydroxysterene (PHS)-based chemically amplified negative resist for EPL. To evaluate the resist sensitivity and the resolution, we prepared the PHS-based negative resists with PAGs of various quantum yields of acid generation, which were the onium-salt- type PAG, the imide-type PAG, and the alkylbenzene-type PAG. The cross-linker was the melamine-type one. Two simultaneously obtain a high sensitivity of less than 10.0 (mu) C/cm2 and a high resolution of less than 0.10 micrometer, a PHS-based negative resist with the imide-type PAG was most preferable. With this resist, we successfully obtained 0.08-micrometer gate line patterns (128 K sub-array of DRAM), exposed by one 250 X 250 micrometer2 EB shot using a 100-kV EB projection experimental column. In addition, the throughput was estimated to be 30 wafers/hour (8' (phi) ) or more.
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