In this study we investigated the influence of the deposition technique on the surface topology and the resulting device performance in organic thin film transistors (OTFT). We varied the parameters of flexographic and gravure printing for the organic semiconductor (OSC) and did multilayer gravure printing for the dielectric, respectively. Therefore, we manufactured transistors in bottom contact top gate architecture and compared them to spin coated samples. As investigation tool for OTFTs, the charge carrier velocity distribution is correlated with the optical characteristics of the printed layers. We found a dependency of the printing technique on the surface topology of the semiconductor and, due to the resulting increase of the channel length, a broadening of the charge carrier velocity distribution. For the dielectric we found a dependency on the layer thickness which seems to be independent from the deposition technique.
For the development of circuits consisting of organic thin film transistors (OTFT) with satisfying yield, a stable and reliable process is necessary. This can be achieved by eliminating failure mechanisms and understanding the charge transport phenomena in the individual device. Following the way of a charge through the device, we start with the investigation of the influence of the Schottky barrier height and contact morphology on the device performance by finite-elements simulations. It could be verified that the charge injection limiting contact resistance can be decreased by two orders of magnitude by reducing the thin oxide layer at the source and drain contacts and improving the semiconductor layer morphology at their vicinity. Second, we present an analytical closed-form solution of the OTFT channel potential used for Monte-Carlo charge transport simulations and compute current-voltage and transient response characteristics out of it. In a next step, the influence of the deposition process on the layer interface is investigated. Therefore, velocity distribution measurements of the charge carriers lead to a simulation model with varying disorder, depending on the layer surfaces and deposition techniques. Afterwards, leakage currents through the gate dielectric can be described by a poor conducting semiconductor model in the finite-elements framework. Leakage currents increase power consumption in circuits and, what is more critical, can lead to a total failure of the OTFT. However, they can be influenced by the number of deposited dielectric layers and charge injection supporting self-assembled monolayers at the source and drain contacts. These findings lead to circuit building blocks for an organic device library whereupon still existing performance fluctuations can be coped with Monte-Carlo circuit simulations.
A novel smart-sensor architecture is proposed, capable to segment and recognize characters in a monochrome image. It is capable to provide a list of ASCII codes representing the recognized characters from the monochrome visual field. It can operate as a blind's aid or for industrial applications. A bio-inspired cellular model with simple linear neurons was found the best to perform the nontrivial task of cropping isolated compact objects such as handwritten digits or characters. By attaching a simple outer-totalistic cell to each pixel sensor, emergent computation in the resulting cellular automata lattice provides a straightforward and compact solution to the otherwise computationally intensive problem of character segmentation. A simple and robust recognition algorithm is built in a compact sequential controller accessing the array of cells so that the integrated device can provide directly a list of codes of the recognized characters. Preliminary simulation tests indicate good performance and robustness to various distortions of the visual field.
Besides foundry facilities, CAD-tools are also required to move microsystems from research prototypes to an industrial market. CAD tools of microelectronics have been developed for more than 20 years, both in the field of circuit design tools and in the area of TCAD tools. Usually a microelectronics engineer is involved only in one side of the design: either he deals with application design or he participates in the manufacturing design, but not in both. This is one point that is to be followed in case of microsystem design, if higher level of design productivity is expected. Another point is that certain standards should also be established in case of microsystem design too: based on selected technologies a set of standard components should be predesigned and collected in a standard component library. This component library should be available from within microsystem design frameworks which might well be established by a proper configuration and extension of existing IC design frameworks. A very important point is the development of proper simulation models of microsystem components that are based on e.g. the FEM results of the predesign phase and are provided in the form of an analog VHDL script. After detailing the above mentioned considerations we discuss the development work concerning a microsystem design framework. Its goal is to provide a set of powerful tools for microsystem application designers. This future framework will be composed of different industry-standard CAD programs and different design databases which in certain cases are completed with special interfaces and special purpose simulation tools.
Conference Committee Involvement (5)
Microelectronics: Design, Technology, and Packaging III
5 December 2007 | Canberra, ACT, Australia
Smart Structures, Devices, and Systems III
11 December 2006 | Adelaide, Australia
Microelectronics: Design, Technology, and Packaging II
12 December 2005 | Brisbane, Australia
Smart Structures, Devices, and Systems II
13 December 2004 | Sydney, Australia
Microelectronics: Design, Technology, and Packaging
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