As device dimensions shrink, the measurement of layer-to-layer overlay is becoming increasingly important. Overlay is currently measured using target patterns fabricated within scribe lines. However, there are residual errors between the measurement values at the scribe lines and the actual values at the circuit pattern regions. Therefore, in-die overlay measurements using circuit patterns are required for precise overlay control. We have developed an in-die overlay measurement method based on SEM images. The overlay is directly measured by comparing a golden image and a test image captured at the circuit pattern region. Each layer is automatically recognized from the images, and the placement error between the two images is determined and used to calculate the overlay. This enables measurement without a specially designed target pattern or the setting up of measurement cursors. In the simulation experiments, the proposed method has linearity and sensitivity for the sub-pixel-order overlay even if the patterns have size variations. The basic performance of this method was evaluated using a defect review SEM. For advanced memory devices, a measurement repeatability of less than 1.0 nm was achieved, and a reasonable wafer map of the overlay was obtained.
As the pattern size shrinkage, it becomes more important to control the critical size of various pattern shapes at
a semiconductor production line. Recently, in a semiconductor process with 20 nm nodes size or less the common
optical and even EB inspection tool have considerable limitation to detect critical physical defects.
From these backgrounds, we have developed the high-sensitivity fixed point inspection tool based on
Review-SEM as the product accomplishment judgment tool for below 10nm size defects on critical size devices.
We examined the basic performance of this inspection tool, optimized inspection parameters including beam
condition and image processing. Then, the defect detection performance was evaluated using various real advanced
memory device containing various critical defects. In this paper, we report these results and show the effectiveness
of this inspection tool to the advanced memory devices.
The key challenge before extreme ultraviolet lithography is to make defect-free masks, for which it is important to identify the root cause of defects, and it is also necessary to establish suitable critical mask defect size for the production of ULSI devices. We have been developing extreme ultraviolet (EUV) mask infrastructures such as a full-field actinic blank inspection tool and 199 nm wavelength patterned mask inspection tool in order to support blank/mask supplier in reducing blank/mask defects which impact wafer printing. In this paper, by evaluating the printability of programmed phase defects and absorber defects exposed by full-field scanner EUV1, we demonstrate that defect detection sensitivities of actinic blank inspection and patterned mask inspection are higher than that of wafer inspection in HP32nm. The evaluations were done by comparing the detection sensitivities of full-field actinic blank inspection tool, 199 nm wavelength patterned mask inspection tool, and electron beam (EB) wafer inspection tool. And then, based on the native defect analysis of blank/mask, we ascertained that actinic blank inspection and patterned mask inspection are effective in detecting killer defects both at the main pattern and at the light-shield border area.
It is important to control the defect level of the EUV lithography mask because of pellicle-less. We studied the resist
patterned wafer inspection method using EB inspection system.
In this paper, the defect detection sensitivity of EB inspection system is quantified using hp 32 nm line and space
pattern with about 5 nm LWR (Line Width Roughness). Programmed defects of 13 nm narrowing and 10 nm widening
have been detected successfully after the optimization of column and inspection condition. Next, the defects detected by
mask inspection system and EB wafer inspection system were compared and were in good agreement for printed killer
defects. In these results, EB inspection system is proved to be useful for EUV resist inspection.
Further, we evaluated the resist material damage by EB inspection irradiation and indicated the direction of reducing
the shrinkage.
The key challenge before EUVL is to make defect-free masks, for which it is important to identify the root cause of
defects, and it is also necessary to establish suitable critical mask defect size for the production of ULSI devices. Selete
has been developing EUV mask infrastructures such as a full-field actinic blank inspection tool and 199nm wavelength
patterned mask inspection tool in order to support blank/mask supplier in reducing blank/mask defects which impact on
wafer printing. In this paper, by evaluating the printability of programmed phase defects and absorber defects exposed
by full-field scanner EUV1, we demonstrate that defect detection sensitivities of ABI (actinic blank inspection) and PI
(patterned mask inspection) are higher than that of WI (wafer inspection) in HP32nm. The evaluations were done by
comparing the detection sensitivities of full-field actinic blank inspection tool, 199nm wavelength patterned mask
inspection tool, and wafer EB inspection tool. And then, based on the native defect analysis of blank/mask, we
ascertained that actinic blank inspection and patterned mask inspection developed at Selete, are effective in detecting
killer defects both at the main pattern and at light-shield border area.
A method for measuring quantitative resistance of incomplete contact holes in ultralarge scale integrated devices-which uses the brightness of voltage contrast in scanning electron microscope (SEM) images-was proposed. The voltage contrast between a contact hole and the surrounding SiO2 surface was observed by both high and low electron-beam-current SEMs and compared with the resistance of that contact hole measured by a nanoprober. The relationship between the SEM-image brightness and the contact-hole resistance was analyzed theoretically by voltage-contrast simulation based on time-differential equations. It was found that the brightness, within 0
Copper damascene process and interlayer dielectrics with ultra-low permittivity have been introduced for manufacturing future devices with higher function speed. As materials with permittivity values lower than 2.2 are required, several kinds of porous materials have been proposed as candidates. However, these porous materials have been observed to shrink easily during CD (critical dimension) measurements with a CD-SEM. To solve this problem, the mechanism of shrinkage and the solution for damage-free SEM observation condition was studied. The shrinkage caused by different electron beam irradiation conditions in a CD-SEM (S-9260, Hitachi High-Technologies Corporation) was investigated with an atomic force microscope (AFM). The result shows that the shrinkage depends on the energy and the dose of electron irradiation. In addition, the change of chemical states and composition caused by electron beam irradiation was analyzed and the shrinkage mechanism was studied. The optimum electron beam irradiation conditions for damage-free measurement are proposed based on experimental results.
KEYWORDS: Inspection, Semiconducting wafers, Electron beams, Dry etching, Scanning electron microscopy, Selenium, Silicon, Signal detection, Etching, Linear filtering
We developed a technique using electron beams for inspecting contact holes immediately after dry etching and detecting incomplete contact failures. Wafers with deep-submicron contact holes that had high aspect ratios of 10 could be detected during practical inspection time by controlling the charging effect on the wafer surfaces. Measurements of the energy distribution in the secondary electrons exhausted from the bottom of the holes indicated that they were accelerated by the charge-up voltage on the wafer surfaces. Our analysis showed that high-density electron beams must be used to charge the surfaces when the aspect ratio is high. The minimum thickness of the residual SiO2 that could be detected at the bottom of the contact holes was 2 nm using an aspect ratio of 8. Applying this mechanism to optimize the dry etching process in semiconductor manufacturing showed that we could achieve reliable process control.
KEYWORDS: Inspection, Semiconducting wafers, Electron beams, Selenium, Signal detection, Dry etching, Scanning electron microscopy, Silicon, Semiconductor manufacturing, Process control
We developed a technique using electron beams for inspection contact holes immediately after dry etching and detecting incomplete contact failures. Wafers with deep-sub-micron contact \holes that had high-aspect-ratios of 10 could be detected during practical inspection time by controlling the charging effect on the wafer surfaces. Measurements of the energy distribution in the secondary electronics exhausted from the bottom of the holes indicated that they were accelerated by the charge up voltage on the wafer surfaces. Our analysis showed that high-density electron beams must be used to charge the surfaces when the aspect ratio is high. The minimum thickness of the residual SiO2 that could be detected at the bottom of the contact holes was 2 nm using an aspect ratio of 8. Applying this mechanism to optimize the dry etching process in semiconductor manufacturing showed that we could achieve reliable process control.
We used two techniques to determine the sensitivity of a scanning-electron-microscope-based wafer-inspection system in detecting open-contact failures. (1) The correlation between the contact resistance and the brightness of the voltage-contrast image as captured by the system was obtained experimentally. (2) A voltage-contrast simulation was developed and applied to derive a correlation between resistance and brightness from these results. A close agreement between the experimental results and the calculated values was obtained. We succeeded in clarifying the determinants of the sensitivity of open-contact-failure detection. The brightness, over part of its range, appears to be proportional to log(R*Ip) where R is the resistance and Ip is the irradiating electron-beam current. This relationship indicates that the sensitivity of open-contact failure detection is determined by Ip. Control of Ip can be used to improve the voltage contrast, and this, in turn, can improve the sensitivity of detection.
KEYWORDS: Oxides, Electron beams, Resistance, Inspection, Semiconducting wafers, Imaging systems, Scanning electron microscopy, Transmission electron microscopy, Wafer inspection, Analytical research
A new voltage contrast imaging method using single scan of high current electron beam has been developed. This method achieved the automatic inspection system, which detects electrical failures in acceptable amount of time. The sensitivity of the system is evaluated using open failure of via holes. First, the image contrast of poly-Si deposited on defective via holes is measured. Then the cross section of the defects is examined to obtain the correlation between contrast and the thickness of resistive residue at the bottom of the defective via holes. The result shows that this imaging method is capable of detecting 2 nm oxide remaining at the bottom of via.
In this paper, it is described that (1) Various type of SOI wafers have each optimum laser illumination mode, (2) Using this optimum laser illumination, 0.1 - 0.3 micrometer particle detection sensitivity has been achieved. (3) By measuring the noise element of scattered light from SOI surface, failure mode can be determined. The performance of the particle detection for each type of wafer and the result of surface roughness failure is also discussed.
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