We have conducted a study of context-dependent variability for cells in a 45nm library, including both lithography and
stress effects, using the Cadence Litho Electrical Analyzer (LEA) software. Here, we present sample data and address a
number of questions that arise in such simulations. These questions include identification of stress effects causing
context dependence, impact of the number of contexts on the results, and combining lithography-induced variations due
to overlay error with context-dependent variations. Results of such simulations can be used to drive a number of
corrective and adaptive actions, among them layout modification, cell placement restrictions, or optimal design margin
determination.
The impact of lithography-induced systematic variations on the parametric behavior of cells and chips designed on a TI
65nm process has been studied using software tools for silicon contour prediction, and design analysis from contours.
Using model-based litho and etch simulation at different process conditions, contours were generated for the poly and
active layers of standard cells in multiple contexts. Next, the extracted transistor-level SPICE netlists (with annotated
changes in CD) were simulated for cell delay and leakage. The silicon contours predicted by the model-based litho tools
were validated by comparing CDs of the simulated contours with SEM images. A comparative analysis of standard cells
with relaxed design rules and restricted pitch design rules showed that restrictive design rules help reduce the variation
from instance to instance of a given cell by as much as 15%, but at the expense of an area penalty. A full-chip variability
analysis flow, including model-based lithography and etch simulation, captures the systematic variability effects on
timing-critical paths and cells and allows for comparison of the variability of different cells and paths in the context of a
real design.
Pushing optical microlithography towards the 32nm node requires hyper-NA immersion optics in combination with advanced illumination, polarization, and mask technologies. Novel approaches in model-based optical proximity correction (OPC) and sub-resolution assist feature (SRAF) optimization are required to not only produce correct feature shapes at the nominal process condition but also to maintain edge placement tolerances within spec limits under process variations in order to ensure a finite process window. In addition, it is becoming increasingly important to consider interactions between multiple layers when performing correction in order to ensure electrical viability. In this paper we discuss the application of a model based process-window-aware and interlayer-aware integrated OPC system on 32nm node patterns. Process window awareness will be demonstrated for main feature correction by taking into account image-based modeling at multiple defocus and dose conditions. In addition, interlayer-awareness will be demonstrated by correction that takes into account the effects of active width on gate CD and of contact overlap with metal, gate, and active. The results show an improvement over "non-aware" OPC in gate CD control, in contact overlap, and in overall process margin. In addition, PW aware correction is demonstrated to prevent potential catastrophic failures at extreme PW conditions.
It is widely understood that the IC Industry's adherence to Moore's Law is widening the gap
between the wavelength of light used in semiconductor manufacturing and the features that they
define. Increasingly, the patterning community has turned to higher complexity imaging solutions to
fill the gap. This steadily increasing complexity is placing a new burden on lithographers and
resolution enhancement technology engineers to guarantee that the highly complex patterning
strategies will work for all patterns. Traditionally, lithography strategies have been characterized
using relatively simple one-dimensional "litho test patterns." Real circuits are highly randomized
however, and complex two-dimensional interactions are the rule rather than the exception.
This paper extends the paradigm for use of newly available post-OPC verification (POV) technology
to the realm of RET development. We offer a case study where two competing 65-nm logic node
sub-resolution assist feature (SRAF) strategies for poly layer patterning are evaluated on a full chip
using commercially available post-OPC verification technology. We are able to evaluate differences
in CD control process window, SRAF printability (illustrated in Figure 1), MEEF sensitivity, and
catastrophic defect propensity. In several critical cases, we show silicon confirmation of the
simulated results. This methodology allows leveraging of existing full-chip POV technology to
enable the selection of the best SRAF strategy with minimal use of costly split lot silicon.
Perhaps the most challenging level to print moving beyond 65 nm node for logic devices is contact hole. Achieving dense to isolated pitches simultaneously in a single mask print requires high NA with novel low-k1 imaging techniques. In order to achieve the desired dense resolution, off axis illumination (OAI) techniques such as annular and quasar are necessary. This also requires incorporation of sub-resolution assist features for improved semidense to isolated contact margin. We have previously discussed design related issues revolving around asymmetric contact hole printing and misplacement associated with using extreme off axis illumination (OAI). While these techniques offer the appropriate dense margin needed, there are regions of severe asymmetric printing which are unsolvable using optical proximity correction (OPC). These regions are impossible to avoid unless design rule restrictions or new illumination schemes are implemented. We continue this work with discussions revolved around illumination choices for alleviating these regions without losing too much dense margin.
Due to complex interconnect wiring scheme and constraints from process rules, systematic defects such as pattern necking and bridging are a major concern for metal layers. These systematic defects or "weak spots" can be major yield detractors in IC manufacturing if not properly addressed. These defects can occur even in cases where model-based OPC has been implemented, as well as a variety of process rules for margin insurance. Determining how to improve the marginalities or "weak spots" becomes a key factor for enhancing product yields. This paper will address several root causes for pattern induced defects and present solutions to a variety of weak spots including "T-shape," "H-shape," "Thin-Line," and "Bowling Pin" defects during 65nm product development at TI. Through case studies, we demonstrate how to successfully provide DFM (Design for Manufacturing) by using Resolution Enhancement Techniques (RET) tools to avoid and minimize the weak spots. Furthermore, process techniques to improve printability for some of the weak spots as applied to 65nm reticle sets will be discussed. An integrated scheme aiming at optimization of design rules and process rules is proposed.
Among the valid gate pattern strategies for the 65nm technology node, att-PSM offers the advantage in cost and mask complexity over other contenders such as complimentary alt-PSM and chromeless phase lithography (CPL). A combination of Quasar illumination and sub-resolution assist features (SRAFs) provides a through pitch solution with a common depth of focus (DOF) better than 0.25um to support the aggressive scaling in both logic and high density SRAM. A global mask-source optimization scheme is adopted to explore the multi-dimensional space of process parameters and define the best overall solution that includes scanner optics such as NA and illumination, and SRAF placement rules for 1-dimensional line and space patterns through the full pitch range. Gate pattern capabilities in terms of DOF, exposure latitude, mask error enhancement factor (MEEF), optical proximity correction (OPC), CD control, and aberration sensitivity are reported in this paper. Conflict resolution and placement optimization are key to the success of implementation of SRAF to the complex 2-dimensional layouts of random logic. Reasonable CD control can be achieved based on the characterization and simulation of CD variations at different spatial and processing domains from local to across chip, across wafer, wafer-to-wafer, and lot-to-lot. Certain layout restrictions are needed for high performance devices which require a much tighter gate CD distribution. Scanner optimization and enhancement such as DoseMapper are key enablers for such aggressive CD control. The benefits, challenges, and possible extensions of this particular approach are discussed in comparison with other techniques.
Perhaps the most critical lithographic challenge at teh 65 nm node can be found printing contact holes for random logic. Achieving all pitches from dense to isolated simultaneously in a single mask print requires high numerical aperture (NA) with novel low-k1 imaging techniques. As is typical in complex engineering problems, requirements compete against each other. The requirement to achieve the desired dense resolution suggests the use of off axis illumination (OAI) techniques such annular and Quasar. At the same time, the need to meet other figures of merit (FOM) such as depth of focus (DOF) and mask error enhancement factor (MEEF) for larger pitches are strong considerations for choosing the more conventional illumination conditions. Moreover, previously unconsidered FOMs such as contact asymmetry and displacement must now also be strongly considered. In particular, we discuss design limitations which may be incorporated to avoid fundamental patterning issues when using OAI and sub-resolution assist features (SRAF) for printing CT level at 65 nm node.
In this paper we study the effects of changing the operating laser wavelength on the projection lens aberrations of KrF and ArF scanners as measured by the Litel In-Situ Interferometer. Specifically, we quantify the change in 28 individual Zernike coefficients as a function of wavelength as well as the total RMS. Effects on Zernike's exhibiting a field dependent behavior are described in detail. We convert the Z4 terms to Z positions to estimate the displacement of the image plane, and we identify a new chromatic distortion term. Finally, we input the measured wavefronts into a lithographic simulator to estimate the full effects on image placement error.
Recently, an in-situ technique for measuring exposure tool projection lens aberrations was introduced by Litel Instruments. In this study we attempt to gauge the performance of the interferometer through comparison of simulated lithographic patterns using the wavefronts measured by the interferometer, with experimental data collected from printed wafers. Our results compare simulation and experiment for cases of field curvature, lithographic astigmatism, linewidth abnormality, and dense- iso bias. As an additional gauge, we show that the change in the measured focus and 3rd order spherical aberration terms followed the theoretical trend for changing position along the optical axis.
Clearly, all lithography simulation tools comprise models that depend on certain measures of the lithography process as input. In fact, it can be said that these models are only as good as their input. Therefore, the tuning of these models to fit the particular conditions of a certain process is a subject worthy of investigation. In this work, we extend previous efforts to generate `tuned' parameters for the lithography process models within PROLITH/2 by including the evaluation of resist cross-sections under a variety of conditions in our analysis, and by more closely examining the sources of factory-specific tuning problems. Specifically, we identify and quantify error sources related to film thickness measurements, utilize the so-called `Poor- Man's DRM' technique to tune PROLITH's resist and development parameters, and compare the resulting simulations to both swing curves and resist cross-sections of various sizes on multiple substrates. The merit of this tuning approach is evaluated based on these comparisons. We conclude that optimization of simulator parameters is critical for accurate resist profile prediction and that, once optimized, the model provides quantitatively predictive results over a wide range of experimental conditions.
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