We report a systematic study of the feasibility of using directed self-assembly (DSA) in real product design for 7-nm fin field effect transistor (FinFET) technology. We illustrate a design technology co-optimization (DTCO) methodology and two test cases applying both line/space type and via/cut type DSA processes. We cover the parts of DSA process flow and critical design constructs as well as a full chip capable computational lithography framework for DSA. By co-optimizing all process flow and product design constructs in a holistic way using a computational DTCO flow, we point out the feasibility of manufacturing using DSA in an advanced FinFET technology node and highlight the issues in the whole DSA ecosystem before we insert DSA into manufacturing.
KEYWORDS: Picosecond phenomena, Polymethylmethacrylate, System on a chip, Scanning electron microscopy, Image segmentation, Photomasks, Etching, Electron beam lithography, Composites, Directed self assembly
Diminishing error tolerance renders the customization of patterns created through directed self-assembly (DSA) extremely challenging at tighter pitch. A self-aligned customization scheme can be achieved using a hybrid prepattern comprising both organic and inorganic regions that serves as a guiding prepattern to direct the self-assembly of the block copolymers as well as a cut mask pattern for the DSA arrays aligned to it. In this paper, chemoepitaxy-based self-aligned customization is demonstrated using two types of organic-inorganic prepatterns. CHEETAH prepattern for “CHemoepitaxy Etch Trim using a self-Aligned Hardmask” of preferential hydrogen silsesquioxane (HSQ, inorganic resist), non-preferential organic underlayer is fabricated using electron beam lithography. Customized trench or hole arrays can be achieved through co-transfer of DSA-formed arrays and CHEETAH prepattern. Herein, we also introduce a tone-reversed version called reverse-CHEETAH (or rCHEETAH) in which customized line segments can be achieved through co-transfer of DSA-formed arrays formed on a prepattern wherein the inorganic HSQ regions are nonpreferential and the organic regions are PMMA preferential. Examples of two-dimensional self-aligned customization including 25nm pitch fin structures and an 8-bar “IBM” illustrate the versatility of this customization scheme using rCHEETAH.
A viable pattern customization strategy is a critical to continue fin pitch scaling. Analysis shows that a self-aligned customization scheme will be required for fin pitch scaling beyond 20nm. In this paper, we explore scaling of the Tone-Inverted Grapho-Epitaxy technique with 24nm pitch PS-b-PMMA polymer to create groups of fins with self-aligned spaces in between. We discuss material selection, self-aligned customization, and etch processes to form 24-nm-pitch fins on silicon on insulator substrates. We demonstrate two-dimensional pattern customization at 24nm pitch, confirming scalability of this approach. FinFET device integration results at both 28 and 24 nm pitches shows a promising path for continued fin pitch scaling.
S. Engelmann, R. Martin, R. Bruce, H. Miyazoe, N. C. Fuller, W. Graham, E. Sikorski, M. Glodde, M. Brink, H. Tsai, J. Bucchignano, D. Klaus, E. Kratschmer, M. Guillorn
CMOS device patterning for aggressively scaled pitches (smaller than 80nm pitch) faces many challenges. Maybe one of the most crucial issues during device formation is the pattern transfer from a soft mask (carbon based) material into a hard mask material. A very characteristic phenomenon is that mechanical failure of the soft material may be observed. While this was observed first for patterning below 80nm pitch, it becomes increasingly important for even smaller pitches (≤ 40 nm). Further process optimization
by various pre- and post-treatments has enabled robust pattern transfer down to 40nm
pitch. A systematic study of the parameters impacting this phenomenon will be shown.
Other challenges for patterning devices include profile control and material loss during
gate stack patterning and spacer formation. Lastly, initial patterning experiments at an
even more aggressive pitch show that the mechanical failure previously observed for
larger pitches once again becomes an increasingly important issue to consider.
Underlayers (UL), such as organic planarizing layers (OPLs) or spin-on carbon (SOC) layers, play a very important role
in various integration schemes of chip manufacturing. One function of OPLs is to fill in pre-existing patterns on the
substrate, such as previously patterned vias, to enable lithographic patterning of the next level. More importantly, OPL
resistance to reactive ion etch (RIE) processes used to etch silicon-containing materials is essential for the successful
pattern transfer from the resist into the substrate. Typically, the pattern is first transferred into the OPL through a two-step
RIE sequence, followed by the transfer into the substrate by a fluorine-containing RIE step that leaves the OPL
pattern mainly intact. However, when the line/space patterns are scaled down to line widths below 35 nm, it was found
that this last RIE step induces severe pattern deformation ("wiggling") of the OPL material, which ultimately prevents
the successful pattern transfer into the substrate.
In this work, we developed an efficient process to evaluate OPL materials with respect to their pattern transfer
performance. This allowed us to systematically study material, substrate and etch process parameters and draw
conclusions about how changes in these parameters may improve the overall pattern transfer margin.
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