Scaling the cell size of phase change memory (PCM) is crucial for reducing reset current and enabling energy-efficient switching. Because memory arrays have a regular pattern, block copolymer directed self-assembly (DSA) is uniquely suited for reducing patterning costs for future nanoscale PCM. Here, we realize the fabrication and electrical characterization of a PCM array with Ge2Sb2Te5 phase change material featuring 20-nm cells patterned by DSA. Our confined cell PCM devices with ~20 nm bottom contact diameter switch at ~150-200 μA, while maintaining a resistance on/off ratio of ~10. We also discuss some factors for further consideration for improving the limited endurance of such nanoscale confined cell PCM. Our demonstration would inspire further reduction of the PCM cell size below 10 nm using high-χ block copolymers, thus paving the pathway towards ultrahigh density memory.
In the pursuit of alternatives to traditional optical lithography, block copolymer directed self-assembly (DSA) has emerged as a low-cost, high-throughput option. However, issues of defectivity have hampered DSA's viability for large-scale patterning. Recent studies have shown copolymer fill level to be a crucial factor in defectivity, as template overfill can result in malformed DSA structures and poor LCDU after etching. For this reason, it is previously demonstrated the use of sub-DSA resolution assist features (SDRAFs) as a method of evening out template density. In this work, we propose an algorithm to place SDRAFs in random logic contact/via layouts. By adopting this SDRAF placement scheme, we can significantly improve the density unevenness and the resources used are also optimized. This is the first work to investigate the placement of SDRAFs in order to mitigate the DSA density variation problem, and it can be adopted for the mass deployment of DSA.
Major advancements in the directed self-assembly (DSA) of block copolymers have shown the technique’s strong potential for via layer patterning in advanced technology nodes. Molecular scale pattern precision along with low cost processing promotes DSA technology as a great candidate for complementing conventional photolithography. Our studies show that decomposition of via layers with 193-nm immersion lithography in realistic circuits below the 7-nm node would require a prohibitive number of multiple patterning steps. The grouping of vias through templated DSA can resolve local conflicts in high density areas, limiting the number of required masks, and thus cutting a great deal of the associated costs. A design method for DSA via patterning in sub-7-nm nodes is discussed. We present options to expand the list of usable DSA templates and we formulate cost functions and algorithms for the optimal DSA-aware via layout decomposition. The proposed method works a posteriori, after place-and-route, allowing for fast practical implementation. We tested this method on a fully routed 32-bit processor designed for sub-7 nm technology nodes. Our results demonstrate a reduction of up to four lithography masks when compared to conventional non-DSA-aware decomposition.
In recent years, major advancements have been made in the directed self-assembly (DSA) of block copolymers (BCPs). As a result, the insertion of DSA for IC fabrication is being actively considered for the sub-7nm nodes. At these nodes the DSA technology could alleviate costs for multiple patterning and limit the number of litho masks that would be required per metal layer. One of the most straightforward approaches for DSA implementation would be for via patterning through templated DSA, where hole patterns are readily accessible through templated confinement of cylindrical phase BCP materials.
Our in-house studies show that decomposition of via layers in realistic circuits below the 7nm node would require at least many multi-patterning steps (or colors), using 193nm immersion lithography. Even the use of EUV might require double patterning in these dimensions, since the minimum via distance would be smaller than EUV resolution. The grouping of vias through templated DSA can resolve local conflicts in high density areas. This way, the number of required colors can be significantly reduced.
For the implementation of this approach, a DSA-aware mask decomposition is required. In this paper, our design approach for DSA via patterning in sub-7nm nodes is discussed. We propose options to expand the list of DSA-compatible via patterns (DSA letters) and we define matching cost formulas for the optimal DSA-aware layout decomposition. The flowchart of our proposed approach tool is presented.
KEYWORDS: Transmission electron microscopy, Platinum, Interfaces, Silicon, Polymethylmethacrylate, 3D modeling, System on a chip, Scanning electron microscopy, Etching, Directed self assembly
In this paper we address an important topic for the development of block copolymer directed self assembly, which is the lack of the third dimensional information. The three-dimensional shape of the DSA feature directly impacts the ability to transfer the DSA pattern into etched patterns. Through TEM sample preparation by in-situ focused ion beam (FIB) Pt deposition and milling, we show cross-sectional images for the two most elemental building blocks of directed self assembled block copolymers, namely, the single and double-hole (peanut shape) etched in Si structures with great contrast at the interface formed by PS and PMMA. Additionally, a hard-mask single hole structure processed with a different template material is shown as well. Elemental mapping with energy filtered TEM (EFTEM) was shown to assist interpretation of images. 3D reconstruction of the holes formed in the hard-mask sample was performed using dark field (DF) STEM. A reduction in the SOC and SOG thickness was observed post in-situ Pt deposition for the hard mask structure. Further TEM sample preparation improvements will be needed to minimize the compression observed.
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