3D NAND flash scaling relies mainly on increasing vertical stack height, thus putting challenges mostly on film deposition and etch. Among various fabrication steps, high aspect ratio (HAR) ONON channel hole etch remains the most critical step. One unique aspect of the 3D NAND process flow is that nitride film in the ONON pair is a sacrificial layer that is been replaced with W at a later stage. The SiN removal process flow provides opportunities to look at possibilities of optimizing oxide and nitride films at different layers to enable better channel hole etch, such as enlarging bottom hole CD, reducing bowing and twisting in the middle area, and etc. In this paper, we will highlight the approaches and benefits on deposition and etch co-optimization as one potential pathway to overcome barrier in HAR ONON channel hole patterning. Besides ONON HAR, hard mask is another key focus. We will also discuss the possible mask material selection consideration based the overall film properties, etch selectivity and final clean/removability perspectives.
Relentless scaling of advanced integrated devices drives feature dimensions towards values which can be expressed in small multiples of the lattice spacing of silicon. One of the consequences of dealing with features on such an atomic scale is that surface properties start to play an increasingly important role. To encompass both dimensional as well as compositional and structural control, we introduce the term “atomic scale fidelity.” In this paper, we will discuss the challenges as well as new solutions to achieve atomic scale fidelity for patterning etch processes. Fidelity of critical dimensions (CD) across the wafer is improved by means of the Hydra Uniformity System. Wafer, chip and feature level atomic scale fidelity such as etch rate uniformity, aspect ratio dependent etching (ARDE) /1/, selectivity and surface damage can be addressed with emerging atomic layer etching (ALE) approaches /2/.
The extendibility of optical lithography using KrF and ArF exposure tools is still being investigated, even, being demanded strongly now, due to the unforeseen issues, high cost, and general difficulty of NGLs - including F2 and immersion lithography. In spite of these challenges Moore's Law requires continued shrinks and the ITRS roadmap still keeps its aggressive timetable. In order to follow the ITRS roadmap, the resolution must keep improving by increasing the lens NA for optical exposure tools. However, the conventional limit of optical resolution (kpitch=0.5) is very close for the current technologies, perhaps limiting progress unless NGL becomes available quickly. Therefore we need to find a way to overcome this seemingly fundamental limit of optical resolution. In this paper, we propose two practical two-mask /double-exposure schemes for doubling resolution in future lithography. One method uses a Si-containing bi-layer resist, and the other method uses Applied Materials' APF (a removable hard mask). The basic ideas of both methods are similar: The first exposure forms 1:3 ratio L/S patterns in one resist/hard mask layer, then the second exposure images another 1:3 ratio L/S pattern in-between the two lines (or two spaces) formed by the first exposure. The combination of these two exposures can form, in theory, kpitch=0.25 patterns. In this paper, we will demonstrate 70nm L/S pattern (140nm pitch) or smaller by using a NA0.68 KrF Scanner and a strong-RET reticle, which corresponds to kpitch = 0.38 (k1=0.19). We will also investigate the critical alignment and CD control issues for these two-mask/dual-exposure schemes.
193nm lithography has become increasingly important as the critical dimensions of semiconductor devices continue to scale down towards sub 0.10um dimension. From dry etching perspective, however, 193nm resist brings new challenges due to its poorer plasma etch resistance, line edge roughness and lower thickness compared to 248nm DUV resist. Consequently, issues such as line edge roughness and poor profile control were observed after dry etch processing. This paper presents a successful development of advanced 0.1 μm metal gate application using 193nm lithography on Applied Materials’ decoupled plasma etcher DPSII system. The integrated process involves a hard mask open with ex-situ resist strip followed by metal/poly dual gate etching. Process chemistry and process parameters for nitride mask step were thoroughly explored and investigated. With CF4/CHF3 based chemistry, the process achieved a greater then 2:1 selectivity with straight nitride profile and smooth sidewall. Less than 7nm 3-sigma of CD bias uniformity was obtained across the wafer with edge exclusion up to 4mm on a 200mm substrate. Process parameters such as pressure, gas ratio and the total Fluorine-contained flow were proven to be the most influential on resist selectivity, profile and CD control. A careful balance needs to be maintained in order to deliver an overall process. The following W/WN/poly gate etch features a three-step approach that has produced straight profiles, excellent CD control and excellent gate oxide integrity. Post-etch measurement of line edge roughness shows an average of 5nm LER. It was observed LER is a strong function of etch chemistry, reaction regime, etc. A detailed study showing methods to reduce LER is presented in this paper.
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