I review progress in monolithic electronic-photonic platforms, including devices and systems-on-chip (SoCs), for communication applications including in-package I/O, cryogenic data egress and quantum photonic networks. I present developments from Ayar Labs towards Terabit to Petabit scale I/O from a single processor package, including co-packaged photonic I/O chiplets with a commercial FPGA, and 1Tbps from a single chiplet; university research demonstrations of record device performances; a cryogenic photonic data link concept and 4K electronic-photonic transmitter demo that could address the I/O bottleneck of superconducting electronics for future supercomputing platforms; and our efforts on electronic-photonic quantum systems-on-chip (epQSoCs) for photonic quantum networks.
We describe a scalable, tiled optical beam steering aperture based on integrated silicon photonic circuit beam steering tiles. A novel beam steering tile design, the serpentine optical phased array (SOPA), enables high fill factor tiled apertures, very low control complexity, an entirely passive aperture, large field of view, and extremely fast beam steering. The design provides low size, weight, and power, making it scalable to large-area (cm-to-wafer scale) apertures. We show experimental demonstrations of SOPA tiles steering an optical beam in two dimensions (2D) enabling a full 2D raster scan using wavelength sweep alone, and initial tiling and lidar demonstrations.
Silicon-based photonics is mobilizing into a manufacturing industry with specialized integrated circuit design requirements for applications in low power cloud computing, high speed wireless, smart sensing, and augmented imaging. The AIM Photonics Manufacturing USA Institute, which operates the world’s most advanced 300mm semiconductor research fab, has co-developed a Process Design Kit (PDK) in fabless circuit design for these expanding digital and analog applications; however, there currently isn’t available an in-depth curriculum to train engineers (academia, industry) in the AIM PDK process and Electronic Photonic Design Automation (EPDA) software. AIM Photonics Academy, an education initiative of AIM Photonics based at MIT, has collaborated with faculty to create three online MOOC edX courses that (1) introduce integrated photonics devices, and applications performance needs and metrics; and (2) train into the AIM PDK and specialized EPDA tools in a six week design project to lay out an application-specific photonic transceiver. The courses are structured around asynchronous video lectures and exploratory design problems that involve Python and Matlab-based first-principles calculations (systems modeling) or advanced EPDA tools (circuit design and layout). The online MOOC courses can optionally form a tandem blended learning component with two AIM Photonics Academy on-site training programs: the annual AIM Summer Academy one-week intensive program (held every July at MIT), or a photonic integrated circuit testing workshop (the first workshop is planned for fall 2019). These courses are a cornerstone effort at AIM to found and support a specialized cohort community of future integrated photonics designers.
A modular laboratory curriculum with exercises for students and lesson plans for teachers is presented. Fundamentals of basic integrated photonic (IP) devices can be taught, first as a lecture-in-the-lab followed by “hands-on” laboratory measurements. This comprehensive curriculum utilizes data collected from the “AIM Photonics Institute PIC education chip” that was designed specifically for the purpose of education, and was fabricated at AIM SUNY Poly. Training using this modular curriculum will be performed through the AIM Photonics Academy network in New York (NY) and Massachusetts (MA), either as a full semester course or as a condensed boot-camp. A synergistic development and delivery of this curriculum will coherently leverage multiple resources across the network and can serve as a model for education and workforce development in other Manufacturing USA institutes, as well as for overseas partners.
We review recent progress of an effort led by the Stojanović (UC Berkeley), Ram (MIT) and Popović (CU Boulder) research groups to enable the design of photonic devices, and complete on-chip electro-optic systems and interfaces, directly in standard microelectronics CMOS processes in a microprocessor foundry, with no in-foundry process modifications. This approach allows tight and large-scale monolithic integration of silicon photonics with state-of-the-art (sub-100nm-node) microelectronics, here a 45nm SOI CMOS process. It enables natural scale-up to manufacturing, and rapid advances in device design due to process repeatability. The initial driver application was addressing the processor-to-memory communication energy bottleneck. Device results include 5Gbps modulators based on an interleaved junction that take advantage of the high resolution of the sub-100nm CMOS process. We demonstrate operation at 5fJ/bit with 1.5dB insertion loss and 8dB extinction ratio. We also demonstrate the first infrared detectors in a zero-change CMOS process, using absorption in transistor source/drain SiGe stressors. Subsystems described include the first monolithically integrated electronic-photonic transmitter on chip (modulator+driver) with 20-70fJ/bit wall plug energy/bit (2-3.5Gbps), to our knowledge the lowest transmitter energy demonstrated to date. We also demonstrate native-process infrared receivers at 220fJ/bit (5Gbps). These are encouraging signs for the prospects of monolithic electronics-photonics integration. Beyond processor-to-memory interconnects, our approach to photonics as a “More-than- Moore” technology inside advanced CMOS promises to enable VLSI electronic-photonic chip platforms tailored to a vast array of emerging applications, from optical and acoustic sensing, high-speed signal processing, RF and optical metrology and clocks, through to analog computation and quantum technology.
We present the spoked-ring microcavity, a nanophotonic building block enabling energy-efficient, active photonics in
unmodified, advanced CMOS microelectronics processes. The cavity is realized in the IBM 45nm SOI CMOS process –
the same process used to make many commercially available microprocessors including the IBM Power7 and Sony
Playstation 3 processors. In advanced SOI CMOS processes, no partial etch steps and no vertical junctions are available,
which limits the types of optical cavities that can be used for active nanophotonics. To enable efficient active devices
with no process modifications, we designed a novel spoked-ring microcavity which is fully compatible with the
constraints of the process. As a modulator, the device leverages the sub-100nm lithography resolution of the process to
create radially extending p-n junctions, providing high optical fill factor depletion-mode modulation and thereby
eliminating the need for a vertical junction. The device is made entirely in the transistor active layer, low-loss crystalline
silicon, which eliminates the need for a partial etch commonly used to create ridge cavities. In this work, we present the
full optical and electrical design of the cavity including rigorous mode solver and FDTD simulations to design the Qlimiting
electrical contacts and the coupling/excitation. We address the layout of active photonics within the mask set of
a standard advanced CMOS process and show that high-performance photonic devices can be seamlessly monolithically
integrated alongside electronics on the same chip. The present designs enable monolithically integrated optoelectronic
transceivers on a single advanced CMOS chip, without requiring any process changes, enabling the penetration of
photonics into the microprocessor.
We present a new treatment of optical forces, revealing that the forces in virtually all optomechanically variable
systems can be computed exactly and simply from only the optical phase and amplitude response of the system.
This treatment, termed the response theory of optical forces (or RTOF), provides conceptual clarity to the
essential physics of optomechanical systems, which computationally intensive Maxwell stress-tensor analyses
leave obscured, enabling the construction simple models with which optical forces and trapping potentials can
be synthesized based on the optical response of optomechanical systems. A theory of optical forces, based
on the optical response of systems, is advantageous since the phase and amplitude response of virtually any
optomechanical system (involving waveguides, ring resonators or photonic crystals) can be derived, with relative
ease, through well-established analytical theories. In contrast, conventional Maxwell stress tensor methods
require the computation of complex 3-dimensional electromagnetic field distributions; making a theory for the
synthesis of optical forces exceedingly difficult. Through numerous examples, we illustrate that the optical forces
generated in complex waveguide and microcavity systems can be computed exactly through use of analytical
scattering-matrix methods. When compared with Maxwell stress-tensor methods of force computation, perfect
agreement is found.
Sampling rates of high-performance electronic analog-to-digital converters (ADC) are fundamentally limited by the timing jitter of the electronic clock. This limit is overcome in photonic ADC's by taking advantage of the ultra-low timing jitter of femtosecond lasers. We have developed designs and strategies for a photonic ADC that is capable of 40 GSa/s at a resolution of 8 bits. This system requires a femtosecond laser with a repetition rate of 2 GHz and timing jitter less than 20 fs. In addition to a femtosecond laser this system calls for the integration of a number of photonic components including: a broadband modulator, optical filter banks, and photodetectors. Using silicon-on-insulator (SOI) as the platform we have fabricated these individual components. The silicon optical modulator is based on a Mach-Zehnder interferometer architecture and achieves a VπL of 2 Vcm. The filter banks comprise 40 second-order microring-resonator filters with a channel spacing of 80 GHz. For the photodetectors we are exploring ion-bombarded silicon waveguide detectors and germanium films epitaxially grown on silicon utilizing a process that minimizes the defect density.
We describe a proposed new class of optonanomechanical integrated photonic devices that can have self-adaptive behavior and self-adaptive optical frequency response, through the use of optical forces to manipulate their movable parts. We propose applications for this technology, and show how such devices can address the enormous dimensional and thermal sensitivity present in nanophotonic structures. Through synthesis of the optomechanical potential, we propose to design and control either the effective optical, or the mechanical, properties of the nanostructure, such as a giant effective optical nonlinear response, nonlinear dynamics and memory. We show device designs that can trap desired states at picometer resolution. We also describe the design of a novel, self-tuning microcavity design whose moving parts adjust in response to light forces alone to always place the resonance at the wavelength of the incident light over a wide wavelength range. This device concept provides an athermal resonator design (temperature-independent resonance frequency), without use of materials with negative thermooptic coefficients. It could also address a major challenge with conventional strong-confinement (high-index-contrast) integrated photonics - their extreme sensitivities - through a self-locking filter bank and optical cross-connect proposal, that in principle can use arbitrarily low power to trim resonant filter passbands to a wavelength channel grid.
Microphotonic devices employing strong confinement of light are of growing importance for key applications such as
telecommunication and optical interconnects. They have unique and desirable characteristics but their extreme
sensitivity to dimensional variations makes them difficult to successfully implement. Here, we discuss strategies towards
the successful realization of strong confinement devices. We leverage what planar fabrication technology does best:
replicating structures. Although the absolute dimensional control required for successful fabrication of many strong
confinement devices is all but impossible to achieve, we show that surprisingly-high relative dimensional accuracy can
be obtained on structures in proximity of one another on a wafer. This provides an advantage to schemes that are based
on multiple copies of low-complexity structures. These copies can be made nearly identical or with precise relative-dimensional
offsets to achieve the desired function. We quantify the achievable relative dimensional control and discuss
the first demonstration of multistage filters, integrated polarization diversity, and high-order microring-filter banks.
Photonic Analog-to-Digital Conversion (ADC) has a long history. The premise is that the superior noise performance of
femtosecond lasers working at optical frequencies enables us to overcome the bottleneck set by jitter and bandwidth of
electronic systems and components. We discuss and demonstrate strategies and devices that enable the implementation
of photonic ADC systems with emerging electronic-photonic integrated circuits based on silicon photonics. Devices
include 2-GHz repetition rate low noise femtosecond fiber lasers, Si-Modulators with up to 20 GHz modulation speed,
20 channel SiN-filter banks, and Ge-photodetectors. Results towards a 40GSa/sec sampling system with 8bits resolution
are presented.
Photonic circuits based on silicon wire waveguides have attracted significant interest in recent years. They allow strong
confinement of light with moderately low propagation losses. Moreover, the high thermo-optical coefficient of silicon
and the small device size in silicon photonics allow for micro-heaters induced trimming, tuning, and switching with
relatively low power. In this paper, we review our recent progress towards telecom-grade reconfigurable optical add-drop
multiplexers (ROADMs) based on silicon microring resonators. We discuss waveguide and micro-heater design
and fabrication as well as the first demonstration of telecom-grade silicon-microring filters and the first demonstration of
transparent wavelength switching. The reported devices can be employed in numerous optical interconnect schemes.
Advances in femtosecond lasers and laser stabilization have led to the development of sources of ultrafast optical pulse
trains that show jitter on the level of a few femtoseconds over tens of milliseconds and over seconds if referenced to
atomic frequency standards. These low jitter sources can be used to perform opto-electronic analog to digital conversion
that overcomes the bottleneck set by electronic jitter when using purely electronic sampling circuits and techniques.
Electronic Photonic Integrated Circuits (EPICs) may enable in the near future to integrate such an opto-electronic
analog-to-digital converters (ADCs) completely. This presentation will give an overview of integrated optical devices
such as low jitter lasers, electro-optical modulators, Si-based filter banks, and high-speed Si-photodetectors that are
compatible with standard CMOS processing and which are necessary for the implementation of EPIC-chips for advanced
opto-electronic ADCs.
Progress in developing high speed ADC's occurs rather slowly - at a resolution increase of 1.8 bits per decade. This slow progress is mostly caused by the inherent jitter in electronic sampling - currently on the order of 250 femtoseconds in the most advanced CMOS circuitry. Advances in femtosecond lasers and laser stabilization have led to the development of sources of ultrafast optical pulse trains that show jitter on the level of a few femtoseconds over the time spans of typical sampling windows and can be made even smaller. The MIT-GHOST (GigaHertz High Resolution Optical Sampling Technology) Project funded under DARPA's Electronic Photonic Integrated Circuit (EPIC) Program is trying to harness the low noise properties of femtosecond laser sources to overcome the electronic bottleneck inherently present in pure electronic sampling systems. Within this program researchers from MIT Lincoln Laboratory and MIT Campus develop integrated optical components and optically enhanced electronic sampling circuits that enable the fabrication of an electronic-photonic A/D converter chip that surpasses currently available technology in speed and resolution and opens up a technology development roadmap for ADC's. This talk will give an overview on the planned activities within this program and the current status on some key devices such as wavelength-tunable filter banks, high-speed modulators, Ge photodetectors, miniature femtosecond-pulse lasers and advanced sampling techniques that are compatible with standard CMOS processing.
Air trench structure for reduced-size bends in low (Δn=0.01-0.1) and medium (Δn=0.1-0.3) index contrast waveguides is proposed. Local high index contrast at bends is achieved by introducing air trenches. An air trench bend consists of cladding tapers to avoid junction loss, providing adiabatic mode shaping between low and high index contrast regions. Drastic reduction in effective bend radius is achieved. We present FDTD simulations of bends in representative silica index contrasts, fabrication scheme and waveguide loss measurement results using Fabry-Perot loss measurement technique. We employed CMOS compatible processes to realize air trench bends and T-splitters to achieve low production cost and high yield. A simple, compact waveguide and T-splitter are fabricated and evaluated. The loss measurement results show that losses are consistent with theoretical simulations. By using air trench waveguides, other applications such as BioMEMS (e.g. Evanescent-field sensor) or EDWA can be realized.
Sharp bends in low index contrast waveguides using tapered air trenches are proposed. To minimize cladding-trench junction loss, cladding tapers are designed to provide adiabatic mode shaping between low and high index contrast regions. Drastic reduction in effective bend radius is predicted. We present 2D FDTD/EIM simulations of bends in representative silica index contrasts. Substrate loss in air trenches of finite depth is investigated, and the required trench depth, given an acceptable substrate loss, is calculated. Fabrication steps are described.
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