With the use of Inverse Lithography techniques (ILT) becoming more relevant for advanced mask lithography, layouts that rely heavily on curvilinear patterns are increasingly more prevalent. Aside from the substantial increase in data volume, the error budgets in the manufacturing of the smallest printed features have decreased considerably and proximity effects once relegated to noise are now in need of careful correction. The correction of these curvilinear masks must be preceded a mask model and, therefore, it is key to procure a fast and accurate method for predicting the mask distortions. In order to meet this challenge, Synopsys has drawn from its related experience in the OPC space to offer a modeling tool that goes beyond the traditional metrology CD-based methodology by relying on the information along the entire edge of the mask shapes. This contour-based approach is complemented with an Advanced Regression step that provides an additional level of optimization of the model parameters and can substantially improve its prediction accuracy. The result is a practical and precise mask modeling tool with a high level of automation. This paper demonstrates the capabilities of this mask modeling solution to a sample of curvilinear and advanced Manhattan layouts.
Currently advanced DRAM design is beyond ArFi resolution limit, especially for the challenging processes in memory cell and core circuit pattern [1]. When devices keep shrinking, multi-patterning with ArFi becomes more and more difficult to reach the process requirements in terms of pattern decomposition, process window loss with complex process integration, defect, and immersion resolution limits. Besides multi-patterning also suffers design cost, mask learning cycle and layout restriction. Currently 0.33NA EUV can provide 16nm pattern single exposure and cover all design circuit requirement. High resolution enhances 2D pattern process window for friendly layout design and better OVL control so it is a good choice to introduce EUV process for DRAM manufacturing.
We evaluate to apply EUV in memory cell instead of the two possible solutions of SADP with cut layer and LELE trimming with multi-mask to simplify processes. Memory cell is periodic main feature for the most area on a mask and dominates the most EUV OPC run time in full shot correction. In this paper we try to find a best way to handle cell area OPC and evaluate single mask to accomplish memory cell patterning.
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