In this paper we will report on the most recent immersion scanner innovations to improve scanner matching overlay. These are realized by improvements in e.g. optical column distortion, wafer alignment and system-metrology. We will elaborate on scanner solutions for wafer handling/chucking of warped wafers. Furthermore, to enable cost-of-ownership reduction, system design implementations driving larger scanner productivity (wafer per hour) will be presented.
The foundations of leading edge DRAM manufacturing are built on accurate EUV lithography exposures in close synergy with cutting-edge immersion layers as well as advanced patterning schemes (e.g. self-aligned multiple patterning). Final device yield critically depends on the subsequent and accurate stacking of multiple layers with device features of precise width and edge placement. To support the ever-decreasing requirements for both the EUV as well as the DUV, (edge) placement accuracy, scanner enhancements are required on both platforms. In this paper we report on the improvements of the NXT:2100i immersion scanner to further reduce the (edge) placement errors within the die (intra-field) and across the full wafer (inter-field). The NXT:2100i incorporates a new projection optics with built-in distortion manipulator that extends the intra-field correction capability for both X and Y directions. The external overlay interface is extended with the distortion manipulator degrees of freedom to handle high spatial frequent distortion data of a to-be-matched scanner or high spatial frequent overlay fingerprints measured by after develop or after etch metrology. Thermal conditioning of the reticle is improved with a fast conditioned internal reticle library resulting in lower reticle-to-reticle temperature variation. Improved lens metrology (aberrations) and reticle align accuracy (alignment/overlay) is achieved with a better integrated image sensor. Improved alignment accuracy and reduced alignment process dependencies for wafer alignment are realized with 12-colors parallel measurements and by adding more alignment marks measurements at the wafer measure side without throughput impact. In concert with the hardware components, various software algorithms are updated, yielding improved inter- and intra-field overlay setup and improved reticle heating induced overlay. We will detail the specific module performance items as well as the system performance of the NXT:2100i scanner, both in reference (DRAM relevant overlay) to DUV as well as to EUV scanners.
As overlay tolerances tighten node-over-node, the measurement and control of overlay has progressed from the low (spatial) frequent domain toward higher spatial frequencies. At present up to 3rd order in the (non-scanning) slit direction can be addressed on high end systems. With the introduction of an advanced distortion-manipulator on an ArFi immersion scanners a significant improvement in the spatial frequency of overlay control can be achieved. This actuator will now enable at least up to 9th order lens distortion manipulation and control in the (non-scanning) slit direction, with future extendibility to on-the-fly adjustments while scanning. The manipulator setup and distortion control is fully incorporated in the scanner software and allows for lens fingerprint optimization, better dynamic lens heating control, and scanner stability control to maintain overlay performance over time. Also an external scanner overlay optimization interface is made available that enables machine-to-machine matching within the immersion platform as well as for cross-matching to the EUV platform. Via this interface also high spatial-frequent process corrections can be send to the scanner. In this paper, we will show the capability of the scanner-integrated distortion manipulator on abovementioned aspects using on-scanner aberration metrology, and in-resist distortion and overlay metrology.
The market transition from 2D to 3D-NAND in recent years requires strict focus control and monitoring solutions. ASML’s μDBF targets (micro Diffraction Based Focus) enable on-product focus measurement which can be used to optimize scanner correction. Additionally, dense computational focus maps can be generated by combining μDBF measurements with scanner metrology such as non-correctable leveling error. This paper discusses the focus variability observed on memory layers through on product focus monitoring. This work will show how exposure at best focus can be performed for immersion lithography in the case of strong focus fingerprints. Focus monitoring data from μDBF and computational focus metrology will be used to generate and apply corrections on two 3D-NAND layers.
All wafers moving through a microchip nanofabrication process pass through a lithographic apparatus for most, if not all, layers. With a lithographic apparatus providing a massive amount of data per wafer, this paper will outline how physicsbased models can be used to refine UVLS (ultraviolet level sensor) metrology into four unique inputs for use in a deep learning network. Due to the multi-dimensional cross correlation of our deep learning network, we then show that training to a sparse overlay layout with dense inputs results in a hyper dense overly signature. On a testing dataset blind to the training we show that the accuracy of the predictive computational overlay metrology can capture R2 up to 0.81 of the signature in overlay Y. As a real-world application, we outline how our predictive computational overlay metrology can then be used to designate which wafer combinations, coming from the TWINSCAN system, should have overlay measured with a YieldStar system for possible use with APC (advanced process control).
Immersion lithography is being extended beyond the 10-nm node and the lithography performance requirement needs to be tightened further to ensure good yield. Amongst others, good on-product focus control with accurate and dense metrology measurements is essential to enable this. In this paper, we will present new solutions that enable onproduct focus monitoring and control (mean and uniformity) suitable for high volume manufacturing environment. We will introduce the concept of pure focus and its role in focus control through the imaging optimizer scanner correction interface. The results will show that the focus uniformity can be improved by up to 25%.
With the increase of litho-etch steps the industry requires metrology to deliver solutions to improve throughput of overlay measurements without impacting accuracy. ASML’s YieldStar 350E is capable of utilizing targets, which can measure the overlay of multiple layers simultaneously. For the work discussed in this paper, an evaluation is performed on Logic product wafers using both single-layer and multi-layer (MLT) quad type targets (able to capture up to four litho-etch steps). Different target types were compared in terms of Move-and-Acquire (MA) time, residual and matching to SEM. Using the MLT targets, an MA time improvement of 56% was demonstrated on the singlelayer. The maximum delta between the overlay residual among the YieldStar targets after applying an high order model was shown to be 0.05 nm. In comparison to after-etch overlay, the correlation of the MLT target was determined with an R2 >; 0.95 using a set-get wafer with induced 10 nm overlay range. On a normal production wafer, the correlation was R2 > 0.67, which is high on a wafer without induced overlay. The comparison of modeling parameters between SEM and MLT targets shows a good match (< 0.16nm) as well.
Overlay metrology target design is an essential step prior to performing overlay measurements. This step is done through the optimization of target parameters for a given process stack. A simulation tool is therefore used to improve measurement performances. This work shows how our Metrology Target Design (MTD) simulator helps significantly in the target design process. We show the role of film and Optical CD measurements in improving significantly the fidelity of the simulations. We demonstrate that for various target design parameters we are capable of predicting measured performance metrics by simulations and correctly rank various designs performances.
Advanced design nodes require more complex lithography techniques, such as double patterning, as well as advanced
materials like hard masks. This poses new challenge for overlay metrology and process control. In this publication
several step are taken to face these challenges. Accurate overlay metrology solutions are demonstrated for advanced
memory devices.
Overlay in lithography becomes much more challenging due to the shrink of device node and multi-patterning approach. Consequently, the specification of overlay becomes tighter, and more complicated overlay control methods like high order or field-by-field control become mandatory. In addition, the tight overlay specification starts to raise another fundamental question: accuracy. Overlay inaccuracy is dominated by two main components: one is measurement quality and the other is representing device overlay. The latter is because overlay is being measured on overlay targets, not on the real device structures. We investigated the following for accurate overlay measurement: optimal target design by simulation; optimal recipe selection using the index of measurement quality; and, the correlation with device pattern’s overlay.
Simulation was done for an advanced memory stack for optimal overlay target design which provides robustness for the process variation and sufficient signal for the stack. Robustness factor and sufficient signal factor sometimes contradicting each other, therefore there is trade-off between these two factors. Simulation helped to find the design to meet the requirement of both factors. The investigation involves also recipe optimization which decides the measurement conditions like wavelength. KLA-Tencor also introduced a new index which help to find an accurate measurement condition. In this investigation, we used CD-SEM to measure the overlay of device pattern after etch or decap process to check the correlation between the overlay of overlay mark and the overlay of device pattern.
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