The pitch-splitting of patterns using the litho-etch-litho-etch double patterning technique (DPT) may be
required at the 22nm node. By splitting the layout into 2 masks, DPT introduces some new potential failure
mechanisms. These new failure mechanisms can occur if the layer decomposition and subsequent OPC fail
to account for interlayer misalignment and corner rounding of the decomposed masks. This paper will
suggest novel solutions which can be taken during the OPC step to account of interlayer misalignment and
corner rounding at decomposed edges. These methods will be shown to produce improved process window
and reduced sensitivity to misalignment compared to a conventional OPC without interlayer awareness.
The 22nm node will be patterned with very challenging Resolution Enhancement Techniques (RETs) such
as double exposure or double patterning. Even with those extreme RETs, the k1 factor is expected to be
less than 0.3. There is some concern in the industry that traditional edge-based simulate-then-move Optical
Proximity Correction (OPC) may not be up to the challenges expected at the 22nm node. Previous work
presented the advantages of a so-called inverse OPC approach when coupled with extreme RETs or
illumination schemes. The smooth mask contours resulting from inverse corrections were shown not to be
limited by topological identity, feedback locality, or fragment conformity. In short, inverse OPC can
produce practically unconstrained and often non-intuitive mask shapes. The authors will expand this
comparison between traditional and inverse OPC to include likely 22nm RETs such as double dipole
lithography and double patterning, comparing dimensional control through process window for each OPC
method. The impact of mask simplification of the inverse OPC shapes into shapes which can be reliably
manufactured will also be explored.
One of the challenges associated with shrinking design dimensions is finding photomask inspection settings which
achieve sufficient defect detection capabilities while supporting aggressive Optical Proximity Correction (OPC). The
most recent technology nodes require very aggressive and advanced Resolution Enhancement Techniques (RETs) which
involve printing small features that are challenging for mask inspection tools. We examine the problems associated with
constraining Models-Based OPC with mask inspection driven rules. We give examples of a 45nm technology node
contact layer design which will receive sub-optimal OPC treatment due to mask inspection constraints. We then take the
mask defect specification typically used for this mask layer, and use Monte Carlo simulation methods to place minimum
sized simulated defects in various locations in close proximity to these sensitive layouts. Simulations of the optimal OPC
are compared to optimal OPC with defects, and to the sub-optimal constrained OPC. Using knowledge about the
frequency of small defects on masks, one can compare the risks associated with small mask defects to the risks
associated with sub-optimal OPC. This exercise demonstrates that there are some instances where mask rules based on
inspection capabilities and defect sensitivity alone can be problematic, and that OPC requirements need to be taken into
account when choosing a defect specification and an inspection strategy. We conclude by proposing a strategy for
balancing these requirements in a practical manner.
For a robust OPC solution, it is important to isolate and characterize the detractors from high quality printability.
Failure in correctly rendering the design intent in silicon can have multiple causes. Model inability in predicting
lithographic and process implications is one of them. Process model accuracy is highly dependant on the quality of data
used in the calibration phase of the model. Structures encountered during the OPC simulation that have not been
included in the calibration patterns, or even structures somewhat similar to those used in calibration, are some times
incorrectly predicted. In this paper a new method for studying VT5 model coverage during OPC simulations is
investigated. The aerial image parameters for a large number of test structures used for model calibration are first
calculated. A novel sorting and data indexing algorithm is then applied to classify the computed data into fast accessible
look-up tables. These tables are loaded in the beginning of a new OPC simulation where they are used as a reference for
comparing aerial image parameters calculated for new design fragments. Such new approach enables real time
classification of design fragments based on how well covered they are by the VT5 model. Employing this method
avoids catastrophic misses in the correction phase and allows for a robust approach to MBOPC.
Current state-of-the-art OPC (optical proximity correction) for 2-dimensional features consists of optimized
fragmentation followed by site simulation and subsequent iterations to adjust fragment locations and
minimize edge placement error (EPE). Internal and external constraints have historically been available in
production quality code to limit the movement of certain fragments, and this provides additional control for
OPC. Values for these constraints are left to engineering judgment, and can be based on lithography
process limitations, mask house process limitations, or mask house inspection limitations. Often times
mask house inspection limitations are used to define these constraints. However, these inspection
restrictions are generally more complex than the 2 degrees of freedom provided in existing standard OPC
software. Ideally, the most accurate and robust OPC software would match the movement constraints to
the defect inspection requirements, as this prevents over-constraining the OPC solution.
This work demonstrates significantly improved 2-D OPC correction results based on matching movement
constraints to inspection limitations. Improvements are demonstrated on a created array of 2D designs as
well as critical level chip designs used in 45nm technology. Enhancements to OPC efficacy are proven for
several types of features. Improvements in overall EPE (edge placement error) are demonstrated for
several different types of structures, including mushroom type landing pads, iso crosses, and H-bar
structures. Reductions in corner rounding are evident for several 2-dimensional structures, and are shown
with dense print image simulations. Dense arrays (SRAM) processed with the new constraints receive
better overall corrections and convergence. Furthermore, OPC and ORC (optical rules checking)
simulations on full chip test sites with the advanced constraints have resulted in tighter EPE distributions,
and overall improved printing to target.
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