The demand on flexible and stretchable energy harvesting devices is rapidly increasing, driven by the substantial market growth of a wide range of applications including wearables and humane robotics. In this talk, we will demonstrate a deep reactive ion etching based corrugation technique to transform large-scale commercial rigid solar cells with interdigitated back contacts into ultra-flexible and ultra-stretchable cells with negligible degradation in the initial efficiency. The design of the corrugated patterns to achieve the desired performance and characteristics of the solar cells in terms of flexibility, stretchability, specific weight, power output and heat dissipation will be discussed. Finally, the encapsulation of the solar cells for a reliable and mechanically robust performance will be explained.
The quest of advancements in electronics has created life changing impacts on living beings. The miniaturization has been the key over decades, and now we have closely approached the physical limit of scaling a fundamental unit of electronics. New directions in terms of flexibility and stretchability has emerged in electronics towards achieving IoT and IoE applications. Stretchable devices has been fundamentally focused on the interconnect design using serpentine, and spiral design connecting the rigid islands or the rigid integrated circuits on the soft polymeric platform. This trivial design technique creates gaps and voids in the stretched structure which leads to reduction in the pixel density and resolution critically important for display applications. Here, we present a mechanism by means of multi-level architecture to mitigate the gaps and simultaneously retaining high pixel density/resolution in displays. Stress distribution of the fundamental unit cells in these fractal design and stretchable architectures has been optimized to distribute load equally, providing more stretchability compared to restricted when arranged in arrays. The concept of unit cell also enables the reconfigurability of the same array of unit cells to form different shapes, entirely based on how the nodes and the unit cell islands are moved and positioned that can reconfigure from square to elliptical, or triangular or hexagonal geometries.
As we are at the verge of entering the era of Internet-of-Things (IoT), there is a clear need to produce continuous power supply to the huge amount of electronic devices that must be wirelessly interconnected and operate uninterruptedly. At the same time, new mechanical constrains arise from the fact that these devices should be ubiquitous, which leads to the need of lightweight and mechanical compliance to any shape or surface. As an important renewable energy source, a mechanically adaptable thermoelectric generator (TEG) can make use of the usually wasted thermal differences between ambient and technology-users to power-up such systems. With this idea in mind, we have developed a simple approach to fabricate TEGs, based on commonly available substrates (paper or polymers) and assisted through simple folding and cutting techniques (born from origami and kirigami) to form strategic structures (serpentine, helical, spiral, etc.) with the mechanical advantage of foldability and over 100% demonstrated stretchability. The use of these methods and structures allows the mechanical reconfigurability of the devices to, for example, increase the temperature difference in a TEG, thus its power, or allow a more efficient use of area and therefore increase the power density. We will discuss the strategies to effectively integrate folding and cutting techniques with common materials and the basic TEG configuration, as well as demonstrate the devices’ implementation and characterization. Finally, we believe our simple integration approach offers an interesting and versatile methodology, which can be easily extrapolated to new materials and technologies for a greater variety of applications.
Complementary metal oxide semiconductor (CMOS) technology offers batch manufacturability by ultra-large-scaleintegration (ULSI) of high performance electronics with a performance/cost advantage and profound reliability. However, as of today their focus has been on rigid and bulky thin film based materials. Their applications have been limited to computation, communication, display and vehicular electronics. With the upcoming surge of Internet of Everything, we have critical opportunity to expand the world of electronics by bridging between CMOS technology and free form electronics which can be used as wearable, implantable and embedded form. The asymmetry of shape and softness of surface (skins) in natural living objects including human, other species, plants make them incompatible with the presently available uniformly shaped and rigidly structured today’s CMOS electronics. But if we can break this barrier then we can use the physically free form electronics for applications like plant monitoring for expansion of agricultural productivity and quality, we can find monitoring and treatment focused consumer healthcare electronics – and many more creative applications. In our view, the fundamental challenge is to engage the mass users to materialize their creative ideas. Present form of electronics are too complex to understand, to work with and to use. By deploying game changing additive manufacturing, low-cost raw materials, transfer printing along with CMOS technology, we can potentially stick high quality CMOS electronics on any existing objects and embed such electronics into any future objects that will be made. The end goal is to make them smart to augment the quality of our life. We use a particular example on implantable electronics (brain machine interface) and its integration strategy enabled by CMOS device design and technology run path.
Current developments on enhancing our smart living experience are leveraging the increased interest for novel systems that can be compatible with foldable, wrinkled, wavy and complex geometries and surfaces, and thus become truly ubiquitous and easy to deploy. Therefore, relying on innovative structural designs we have been able to reconfigure the physical form of various materials, to achieve remarkable mechanical flexibility and stretchability, which provides us with the perfect platform to develop enhanced electronic systems for application in entertainment, healthcare, fitness and wellness, military and manufacturing industry. Based on these novel structural designs we have developed a siliconbased network of hexagonal islands connected through double-spiral springs, forming an ultra-stretchable (~1000%) array for full compliance to highly asymmetric shapes and surfaces, as well as a serpentine design used to show an ultrastretchable (~800%) and flexible, spatially reconfigurable, mobile, metallic thin film copper (Cu)-based, body-integrated and non-invasive thermal heater with wireless controlling capability, reusability, heating-adaptability and affordability due to low-cost complementary metal oxide semiconductor (CMOS)-compatible integration.
Evolution in transistor technology from increasingly large power consuming single gate planar devices to energy efficient multiple gate non-planar ultra-narrow (< 20 nm) fins has enhanced the scaling trend to facilitate doubling performance. However, this performance gain happens at the expense of arraying multiple devices (fins) per operation bit, due to their ultra-narrow dimensions (width) originated limited number of charges to induce appreciable amount of drive current. Additionally arraying degrades device off-state leakage and increases short channel characteristics, resulting in reduced chip level energy-efficiency. In this paper, a novel nanotube device (NTFET) topology based on conventional group IV (Si, SiGe) channel materials is discussed. This device utilizes a core/shell dual gate strategy to capitalize on the volume-inversion properties of an ultra-thin (< 10 nm) group IV nanotube channel to minimize leakage and short channel effects while maximizing performance in an area-efficient manner. It is also shown that the NTFET is capable of providing a higher output drive performance per unit chip area than an array of gate-all-around nanowires, while maintaining the leakage and short channel characteristics similar to that of a single gate-all-around nanowire, the latter being the most superior in terms of electrostatic gate control. In the age of big data and the multitude of devices contributing to the internet of things, the NTFET offers a new transistor topology alternative with maximum benefits from performance-energy efficiency-functionality perspective.
With the emergence of cloud computation, we are facing the rising waves of big data. It is our time to leverage such opportunity by increasing data usage both by man and machine. We need ultra-mobile computation with high data processing speed, ultra-large memory, energy efficiency and multi-functionality. Additionally, we have to deploy energy-efficient multi-functional 3D ICs for robust cyber-physical system establishment. To achieve such lofty goals we have to mimic human brain, which is inarguably the world’s most powerful and energy efficient computer. Brain’s cortex has folded architecture to increase surface area in an ultra-compact space to contain its neuron and synapses. Therefore, it is imperative to overcome two integration challenges: (i) finding out a low-cost 3D IC fabrication process and (ii) foldable substrates creation with ultra-large-scale-integration of high performance energy efficient electronics. Hence, we show a low-cost generic batch process based on trench-protect-peel-recycle to fabricate rigid and flexible 3D ICs as well as high performance flexible electronics. As of today we have made every single component to make a fully flexible computer including non-planar state-of-the-art FinFETs. Additionally we have demonstrated various solid-state memory, movable MEMS devices, energy harvesting and storage components. To show the versatility of our process, we have extended our process towards other inorganic semiconductor substrates such as silicon germanium and III-V materials. Finally, we report first ever fully flexible programmable silicon based microprocessor towards foldable brain computation and wirelessly programmable stretchable and flexible thermal patch for pain management for smart bionics.
Today’s information age is driven by silicon based electronics. For nearly four decades semiconductor industry has perfected the fabrication process of continuingly scaled transistor – heart of modern day electronics. In future, silicon industry will be more pervasive, whose application will range from ultra-mobile computation to bio-integrated medical electronics. Emergence of flexible electronics opens up interesting opportunities to expand the horizon of electronics industry. However, silicon – industry’s darling material is rigid and brittle. Therefore, we report a generic batch fabrication process to convert nearly any silicon electronics into a flexible one without compromising its (i) performance; (ii) ultra-large-scale-integration complexity to integrate billions of transistors within small areas; (iii) state-of-the-art process compatibility, (iv) advanced materials used in modern semiconductor technology; (v) the most widely used and well-studied low-cost substrate mono-crystalline bulk silicon (100). In our process, we make trenches using anisotropic reactive ion etching (RIE) in the inactive areas (in between the devices) of a silicon substrate (after the devices have been fabricated following the regular CMOS process), followed by a dielectric based spacer formation to protect the sidewall of the trench and then performing an isotropic etch to create caves in silicon. When these caves meet with each other the top portion of the silicon with the devices is ready to be peeled off from the bottom silicon substrate. Release process does not need to use any external support. Released silicon fabric (25 m thick) is mechanically flexible (5 mm bending radius) and the trenches make it semi-transparent (transparency of 7%).
KEYWORDS: System on a chip, Transistors, Solar cells, Laser induced breakdown spectroscopy, Microsoft Foundation Class Library, Nanotechnology, Ions, Solar energy, CMOS technology, Nanowires
In today's world, consumer driven technology wants more portable electronic gadgets to be developed, and the next big
thing in line is self-powered handheld devices. Therefore to reduce the power consumption as well as to supply sufficient
power to run those devices, several critical technical challenges need to be overcome:
a. Nanofabrication of macro/micro systems which incorporates the direct benefit of light weight (thus portability), low
power consumption, faster response, higher sensitivity and batch production (low cost).
b. Integration of advanced nano-materials to meet the performance/cost benefit trend. Nano-materials may offer new
functionalities that were previously underutilized in the macro/micro dimension.
c. Energy efficiency to reduce power consumption and to supply enough power to meet that low power demand.
We present a pragmatic perspective on a self-powered integrated System on Chip (SoC). We envision the integrated
device will have two objectives: low power consumption/dissipation and on-chip power generation for implementation
into handheld or remote technologies for defense, space, harsh environments and medical applications. This paper
provides insight on materials choices, intelligent circuit design, and CMOS compatible integration.
Aggressive CMOS transistor scaling requirements have motivated the IC industry to look beyond simply reducing the
film thickness or implementing different gate stack materials towards fundamentally redesigning the transistor
architecture by forcing the silicon channel to protrude upwards from the planar (2D) substrate. These 3D transistors,
namely FinFETs, ideally offer at least a 2X improvement in the drive current since more than one surface is available,
for which the minority carrier population can be adjusted by an applied voltage. However, the ability to modulate this
voltage is known to suffer due to the non-uniform film deposition on the three sides of the Si Fin. This concern is of
immediate interest because it impedes device performance and future integration since subtle differences among the
thicknesses on each side of the Fin will negatively impact threshold voltage and the capability to tune the effective work
function. It is therefore necessary to have an in-line metrology capability that can properly characterize and understand
the deposition of both the high-k and metal gate film on the sidewalls of the Fin in order for FinFETs to ultimately
replace planar CMOS devices. We will report on the ability of scatterometry to accurately measure the high-k and
metal film thickness on the sidewall of the FinFET. The results will be discussed in detail with emphasis on sensitivity
towards fin critical dimension (CD) and sidewall thickness, and comparison of the conclusions reached from the
analysis with cross-sectional transmission electron microscopy (TEM) data.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.