Machine learning has significant potential to help the human designer produce better outcomes. It can also help manage some of the complexity with chip design in advanced nodes. Projects to be discussed include the following.
o Using Bayesian optimization for circuit IP reuse. Analog and custom digital IP reuse is difficult and time-consuming. Professor Franzon's group has built a Bayesian optimization approach involving statistical surrogate models. They have demonstrated by porting a number of designs between nodes, including a BJT to SOI port. The machine learning based approach produced better results than a human designer.
o Using Surrogate modeling for Physical design. Professor Franzon's group has used a machine learning approach to predict Global Router and detailed router results as a function of tool input settings. These models can be used to tune the tool setup for specific outcomes.
o Using Surrogate Modeling and System Identification Modeling to model digital receiver chains. Digital receiver modeling is predict BER of a receiver in the presence of an input signal with a close eye. Professor Franzon's group has used a combination of Surrogate Modeling and System Identification to build such a modeling capability.
o Using deep networks for design rule checking. The team has demonstrated that deep networks can be used instead of Boolen checkers. There is significant potential to close the DFM and custom design productivity gaps.
Structures demonstrating the viability of both the hydraulic and latching Braille dot, and the dielectric elastomer fiber
Braille dot have been fabricated and characterized. A hydraulic proof-of-concept structure has achieved the necessary
volumetric change required to lift a Braille dot over 0.5mm at voltages under 1000V and at speeds under 100ms. Long
bimorphs have been fabricated that demonstrate large tip displacements over 2mm that could be used to mechanically
latch the Braille rod in the 'up' position to achieve the force requirement. The addition of radial prestrain in dielectric
elastomer tubes has reduced the wall thickness and directed the strain in the axial direction which has had a dramatic
impact on their resulting characteristics. The required bias voltage for the dielectric elastomer fiber Braille dot has been
reduced from 15.5kV to 8.75kV while the Braille head tip displacement of a fabricated prototype has almost tripled on
average and now also exceeds the required displacement for a refreshable Braille display. Finally, potential solutions to
the current shortcomings of both designs in meeting all of the requirements for such a display are discussed.
The development of a multiline, refreshable Braille display will assist with the full inclusion and integration of blind
people into society. The use of both polyvinylidene fluoride (PVDF) film planar bending mode actuators and silicone
dielectric elastomer cylindrical tube actuators have been investigated for their potential use in a Braille cell. A liftoff
process that allows for aggressive scaling of miniature bimorph actuators has been developed using standard
semiconductor lithography techniques. The PVDF bimorphs have been demonstrated to provide enough displacement to
raise a Braille dot using biases less than 1000V and operating at 10Hz. In addition, silicone tube actuators have also been
demonstrated to achieve the necessary displacement, though requiring higher voltages. The choice of electrodes and
prestrain conditions aimed at maximizing axial strain in tube actuators are discussed. Characterization techniques
measuring actuation displacement and blocking forces appropriate for standard Braille cell specifications are presented.
Finally, the integration of these materials into novel cell designs and the fabrication of a prototype Braille cell are
discussed.
KEYWORDS: Computer aided design, Silicon, Logic, 3D applications, Semiconducting wafers, Digital signal processing, Thermal modeling, 3D modeling, Clocks, Integrated circuits
3D stacking and integration can provide
system advantages equivalent to up to two technology
nodes of scaling. This paper explores memory rich
applications for 3DIC. It shows how memory power
and memory bandwidth can both be improved by an
order of magnitude through 3D integration, and
specifically explores a DSP application.
Ternary Content Addressable Memory (TCAM) has been an emerging technology for fast packet forwarding, commonly
used in longest prefix match routing. Large table size requirements and wider lookup table data widths have led to
higher capacity TCAM designs. However, the fully parallel characteristic of TCAM makes large TCAM design more
challenging and limits its capacity due to intensive power consumption. This paper proposes 3D IC technology as a
solution to reduce the power consumption by reducing the interconnect capacitances of TCAM. In 3D IC, multiple
wafers are stacked on top of each other, and the tiers are vertically connected through 3D vias. 3D vias reduce metal
interconnect lengths and parasitic capacitances, resulting in power reduction. In this paper, 3D vias are used to replace
matchlines, whose transition during parallel search operations is a major source of high power consumption in TCAM.
An analysis of parasitic interconnect capacitance has been done using a quasi-static electromagnetic field simulation
tool, Ansoft's Q3D Extractor, on a TCAM memory core in both conventional 2D IC structure and 3D IC structure with
the process parameters of the MIT Lincoln Labs 0.18μm FDSOI process. Field analysis and spice simulation results
using a capacitance model for interconnects show that a 40% matchline capacitance reduction and a 23% power
reduction can be achieved by using a 3-tier 3D IC structure instead of the conventional 2D approach.
A novel masking technique that enables the complex patterning of metal on any layer of a released MEMS chip is demonstrated. This technique enables a polysilicon only MEMS process to create low-loss RF devices. To illustrate the advantages of post-release metallization, in a polysilicon only MEMS process, a rotating MEMS tunable capacitor that provides a wide and linear tuning range is presented. The core of the design comes from high yield, mechanically proven gear designs from Sandia’s SUMMiT design library. Significant alterations were made to the gear structure to create the final device. Preliminary tests show device capacitance ratios of 1.8:1, with linear tuning. Increased metal deposition to reduce the device air gap, can produce a capacitance ratio over 6:1.
AC Coupled Interconnection (ACCI), in conjunction with buried solder bump technology, provides a method to achieve signal I/O pitches of less than 100 μm and signaling rates greater than 3 Gbps per I/O on integrated circuits, while preserving excellent signal integrity. This paper presents a summary of approaches and status capacitive and inductive versions of AC Coupled Interconnect Systems.
One problem faced by designers utilizing polysilicon based surface micromaching processes is the poor conductivity of polysilicon. Process factors preclude inclusion of metal layers in these processes before the final polysilicon layer is annealed. Adding metal after anneal but before release restricts the metal to only the top layer of the design, making it much less useful for interconnect, and restricting reflective surfaces to the top layer. We present techniques for adding metal after release which avoid some of the usual pitfalls. Application areas for which these techniques could prove useful include RF, Microwave, Optical MEMS, and MEMS devices used in high-speed digital communications. Creating a multilayer metal interconnect is enabled by utilizing a self-masking approach to avoid shorting, and applying e-beam evaporation from a variety of angles. Using this approach, even lower level polysilicon lines can be metallized. Results using two deposition angle recipes on test structures and devices fabricated in a thin film MEMS process are presented.
With the recent surge in popularity of RF and Microwave MEMS many different device topologies are being explored. Some devices provide large changes in capacitance, but lack the ability to provide a linear range of capacitance values between the minimum and maximum values of the device. We present a device design for a low-loss rotating MEMS tunable capacitor that once programmed to the required value consumes no power. This device design is transformed from gear structures currently designed in the SUMMiT process with modifications made so that the device may be used as a varactor. Modifications include alterations of physical structure, drive mechanism for programming capacitance value, and additional post processing steps needed to provide low-loss at RF and Microwave frequencies. Many different device structures are possible each with performance, potential reliability, and potential yield trade offs that must be considered. Post processing is required to add metal to provide sufficiently low loss for high quality components. Since device planarity is critical for operation, a novel post-process metal deposition technique for providing low stress metal was concieved. Additional modifications to compensate for polysilicon warpage are considered for future investigation. Simulation results based on high frequency full wave analysis software show a highly linear tuning range and a capacitance ratio approaching 6 to 1. A model is extracted from the scattering parameters provided by HFSS and then various device sizes and topologies are compared.
Recently, several mechanisms have been proposed as a basis for designing molecular electronic logic switching elements. Many two terminal molecular devices functioning as diodes have been synthesized with responses similar to silicon devices such as rectifying and resonant tunneling diodes. In this paper, the feasibility of integrating these molecular diodes into current circuit architectures is explored. A series of logic gates and a memory element are simulated based on the voltage-controlled current flow method using the Tour-Reed molecular diode exhibiting negative differential resistance (NDR). HSPICE simulation results are used to illustrate the performance of these devices and to quantify additional component and interconnect requirements. Finally, future system design approaches using molecular components are discussed.
We describe a programmable capacitor technology under development at NCSU and its potential application in building programmable interconnect devices useful for system level connectivity functions, phased array beam steering, and RF switching. Crossbars are made from arrays of electrostatically controlled bistable MEMS-based capacitors. These new devices allow faster signaling and consume less power than BiCMOS crossbars. They also allow critical RF components to be shrinked in size substantially. We describe the essential elements of these arrays and present results obtained so far.
KEYWORDS: Field programmable gate arrays, Convolution, Motion estimation, Switching, Image filtering, Data storage, Data processing, Sun, Chemical elements, Switches
Reconfigurable machines have recently been used as co- processors to accelerate the execution of certain algorithms or program subroutines. The problems with the above approach include high reconfiguration time and limited partial reconfiguration. By far the most critical problems are: (1) the small on-chip memory which results in slower execution time, and (2) small FPGA areas that cannot implement large subroutines. Dynamically Programmable Cache (DPC) is a novel architecture for embedded processors which offers solutions to the above problems. To solve memory access problems, DPC processors merge reconfigurable arrays with the data cache at various cache levels to create a multi-level reconfigurable machines. As a result DPC machines have both higher data accessibility and FPGA memory bandwidth. To solve the limited FPGA resource problem, DPC processors implemented multi-context switching (Virtualization) concept. Virtualization allows implementation of large subroutines with fewer FPGA cells. Additionally, DPC processors can parallelize the execution of several operations resulting in faster execution time. In this paper, the speedup improvement for DPC machines are shown to be 5X faster than an Altera FLEX10K FPGA chip and 2X faster than a Sun Ultral SPARC station for two different algorithms (convolution and motion estimation).
This paper presents some results from phase-1 research into developing a beam steerer based on micro-mechanical diffractive elements. The position of these elements is electrostatically controlled, to allow dynamic programming of a 2D phase function. Feasibility prototypes were constructed in the MUMPs polysilicon surface micromachine process.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.