3-stack and 4-stack, 6" dia. multilayered SOI have been fabricated using two different processes, and the bonding ability, thickness uniformity, and stress investigated. High-quality bonding was achieved with good thickness control, independent of the fabrication method used. The stress in the overall structure was controlled by the balance between the combined stress at the oxide silicon interfaces of the SOI buried oxide layers and that exerted by the oxide on the back surface of the handle wafer. An imbalance of 0.5 μm corresponded to a generated bow of about 12 μm. The etch rate of the buried oxide was enhanced along the bonding interface, particularly in the case of an oxide-oxide join, and was found to be strongly dependent on the bond annealing temperature.
In this paper, we have presented the novel method of fabricating multiplayer-stacked SOI (MultiBond). Tight thickness and TTV control was achieved, which allowed the bonding of multiple layers of SOI of up to 4-layer stacks. Investigation of the stress showed that having the handle wafer oxidized at the back significantly reduced the stress by compensating for the buried oxide layers. Study was also made on the effect of incorporating different buried layers on the minority carrier lifetime in the SOI layer. Here, a thermally grown buried oxide layer gave the highest carrier lifetime. We have also investigated the surface defect density with different buried layer materials, and found that samples with tungsten silicide as a buried layer had the highest defect density, while an LPCVD TEOS oxide buried layer showed the lowest level.
The step coverage of dielectrics is important for the microelectronics industry and critical to Micro-machined products and High Voltage MEMS drivers. The techniques used to fabricate MEMS structures require void free refill processes and even film deposition along deep trenches to protect against etch chemistries. High voltage drivers used to actuate MEMS devices benefit from dielectric isolation, which reduces the need for large tub formation between devices. It also enables 'system on chip' solutions for MEMs devices and protection against voltage spikes. This paper presents a process developed at Analog Devices Belfast that enables an LPCVD TEOS furnace to perform a highly conformal trench refill without equipment modification. The conformality is over 95% for 20 micrometer deep trenches and maintains a conformality greater than 85% in 50 micrometer deep trenches. This compares with 75% conformality which is considered excellent for 20 micrometer trench refills obtained using previous LPCVD TEOS processing. The process is shown to have benefits in conformality, breakdown voltage, and stress over standard trench fill processes including Ozone TEOS. The densification of the TEOS film has been optimized for electrical parameters using CV and IV techniques, while XPS, FTIR and spectroscopic ellipsometry are used for physical characterization. Stress is a very important parameter for micro-machining and the conformal TEOS has a film stress which is tensile 30 - 40 MPa as deposited and compressive 100 MPa after densification. The breakdown voltage has been measured at 8.5 MV/cm compared to 7.5 - 9 MV/cm for a typical densified TEOS film and the refractive index is 1.456 compared to 1.465 for a thermal oxide. Analog Devices Belfast is part of the Micro-machined Products division and provides SOI and customized SOI for the MEMs and IC market.
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