Mr. Peter V. Vun Profile

Peter V. Vun

at Macquarie Univ

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Proceedings Article | 21 December 2007 Paper

Geometric dependence of the parasitic components and thermal properties of HEMTs

Peter Vun, Anthony Parker, Simon Mahon, Anthony Fattorini

Proceedings Volume 6798, 67980B (2007) https://doi.org/10.1117/12.759011

KEYWORDS: Field effect transistors, Inductance, Thermal modeling, Instrument modeling, Transistors, Modeling, Circuit switching, Integrated circuit design, Performance modeling, Thermography

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For integrated circuit design up to 50GHz and beyond accurate models of the transistor access structures and intrinsic structures are necessary for prediction of circuit performance. The circuit design process relies on optimising transistor geometry parameters such as unit gate width, number of gates, number of vias and gate-to-gate spacing. So the relationship between electrical and thermal parasitic components in transistor access structures, and transistor geometry is important to understand when developing models for transistors of differing geometries. Current approaches to describing the geometric dependence of models are limited to empirical methods which only describe a finite set of geometries and only include unit gate width and number of gates as variables. A better understanding of the geometric dependence is seen as a way to provide scalable models that remain accurate for continuous variation of all geometric parameters. Understanding the distribution of parasitic elements between the manifold, the terminal fingers, and the reference plane discontinuities is an issue identified as important in this regard. Examination of dc characteristics and thermal images indicates that gate-to-gate thermal coupling and increased thermal conductance at the gate ends, affects the device total thermal conductance. Consequently, a distributed thermal model is proposed which accounts for these effects. This work is seen as a starting point for developing comprehensive scalable models that will allow RF circuit designers to optimise circuit performance parameters such as total die area, maximum output power, power-added-efficiency (PAE) and channel temperature/lifetime.

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