BackgroundThe demand for high-performance semiconductor products has led to reduced wafer feature size, lowered package size, and an ever-thinner die for advanced three-dimensional (3D) packaging. Dies down to a thickness of 5 μm have been demonstrated. One significant barrier is the fragility of the thin dies, their overall thin form factor, and their impact on yield, reliability, and costs.AimWe explore the current state of the art in the current crack stop and outline the shortcomings moving forward for stacked 3D integrated circuits (3DIC).ApproachUsing a theoretical understanding of fracture mechanics and the new biomimetic concept adapted from nature, we show the implementation of the new crack stop insertions in the die frame for a next-generation 3DIC product.ResultsThe proposed crack stop can be easily inserted in the die frame with electronic design automation (EDA) tools using a Python interpreter and has the capability to arrest a crack near its initiation point.ConclusionsWe show the feasibility of the implementation through EDA tools and outline the next step.
The demand for high-performance semiconductor products has increased with no end in sight since the early days of this industry. This product demand phenomenon has continuously pushed the technological frontier to a moving limit for enhanced performance leading to the need for an ever-thinner die for advanced 3D packaging. Die down to a thickness of 5 µm is feasible. The thin die approach may lead to a heterogenous stack of 50 dies, leading to the highest available performance with an unprecedented form factor. One significant barrier is the fragility of the thin die and its impact on yield, reliability, and costs. A comprehensive crack propagation and thin die fragility model that is rich in both theory and application is presented. In this paper, we show an MPW reticle placement with automation that inserts new and specific crack-stop patterns to mitigate the risk of die wafer fracture. We show this method to address die fracture from both the front and the back sides of the wafer, yielding an authentic 3D approach to crack-stop.
This paper presents a novel approach to automatically build frames for 3D chips. These chips may be obtained by stacking multiple dies, but are more often made by a backside wafer processing. This proposed flow works in a single pass and is based on a dedicated constraint-satisfaction software. In addition to the standard placement rules, the different types of constraints used for 3D frames are clearly identified: alignment, overlapping, mirroring. The method to generate separate frames is described. Results and performance obtained in production, for frames involving two different manufacturing processes for wafer front and backside, are detailed.
We propose a new method applied on Multi-Project Wafer (MPW) reticles to reduce thermal-mechanical stress. Wafer bumping processes generate residual thermal-mechanical stress, causing crack and delamination across wide regions on a wafer. In this paper, we show the work achieving optimized metal layer densities and density gradients across the reticle to minimize the stress effects. We propose a new MPW chip placement flow that places chips on an MPW reticle meeting the minimum density gradients as the placement criterion. The flow also performs inter-die dummy metal fills to optimize densities with regard to each chip density. We show intentional crack-stop dummy metal rings the flow generates surrounding a chip. The dummy rings further reduce the propagation of stress cracks. We show the results of optimized density gradients and crack-stop rings across the chips on an MPW reticle.
This paper addresses large dies stitching challenges. Stitching is a way to combine several shots "stitched together" to create a die larger than what can fit on a photomask. This technique that was originally dedicated to advanced research is now more widely used and requires a fully automated industrial flow. Technical constraints come from a number of different actors and results must be shared by even more teams. We will present the methodology used to optimize both the yield and the data exchange between cross-functional teams. We will show how this automated flow can be easily customized to save more silicon thanks to advanced dicing techniques.
Advanced process photolithography masks require more and more controls for registration versus design and critical dimension uniformity (CDU). The distribution of the measurement points should be distributed all over the whole mask and may be denser in areas critical to wafer overlay requirements. This means that some, if not many, of theses controls should be made inside the customer die and may use non-dedicated patterns. It is then mandatory to access the original layout database to select patterns for the metrology process.
Finding hundreds of relevant patterns in a database containing billions of polygons may be possible, but in addition, it is mandatory to create the complete metrology job fast and reliable. Combining, on one hand, a software expertise in mask databases processing and, on the other hand, advanced skills in control and registration equipment, we have developed a Mask Dataprep Station able to select an appropriate number of measurement targets and their positions in a huge database and automatically create measurement jobs on the corresponding area on the mask for the registration metrology system. In addition, the required design clips are generated from the database in order to perform the rendering procedure on the metrology system.
This new methodology has been validated on real production line for the most advanced process. This paper presents the main challenges that we have faced, as well as some results on the global performances.
Design complexity sometimes grows faster than EDA tools performances, and some innovation should be made
on the design flow to guarantee the best possible validation in a reasonable time. This was the challenge we were
facing for the final layout validation of a 3 billions transistors, multi cores chip designed for a 28nm process. The
design backend validation requires multiple tools: the LVS to check connectivity, the DRC to check layout rules
and the ERC to check any risk of power drop among the whole chip. While the 2 first tools are able to deal with
huge designs by using hierarchical approaches, Electrical Rule Checking is much more complicated as the power
routing is generally made flat at the top level of the chip. The classical ERC tools were not able to validate the
power distribution at top level. The power distribution was made through a power grid using two metal layers
and arrays of vias to connect each block at deeper metal layers. The chip is made of 256 processors and has a
quite regular structure so that each module has it own power grid with the same pitch and every thing should
be butting or properly connected at top level. It has then been decided to use a very efficient tool dedicated to
geometrical verification of flat designs (typically a Mask Rule Checker) to check any interruption on power lines
or missing vias in arrays. This paper will describe how this validation was performed as well as the performances
obtained on a 28nm, 3 billions transistors design.
Designing a fully new 256 cores processor is a great challenge for a fabless startup. In addition to all architecture,
functionalities and timing issues, the layout by itself is a bottleneck due to all the process constraints of a 28nm
technology. As developers of advanced layout finishing solutions, we were involved in the design flow of this huge
chip with its 3 billions transistors. We had to face the issue of dummy patterns instantiation with respect to
design constraints. All the design rules to generate the “dummies” are clearly defined in the Design Rule Manual,
and some automatic procedures are provided by the foundry itself, but these routines don’t take care of the
designer requests. Such a chip, embeds both digital parts and analog modules for clock and power management.
These two different type of designs have each their own set of constraints. In both cases, the insertion of dummies
should not introduce unexpected variations leading to malfunctions. For example, on digital parts were signal
race conditions are critical on long wires or bus, introduction of uncontrolled parasitic along these nets are highly
critical. For analog devices such as high frequency and high sensitivity comparators, the exact symmetry of the
two parts of a current mirror generator should be guaranteed. Thanks to the easily customizable features of our
dummies insertion tool, we were able to configure it in order to meet all the designer requirements as well as the
process constraints. This paper will present all these advanced key features as well as the layout tricks used to
fulfill all requirements.
Some chip manufacturing steps lead to non-negligible
process variation at wafer level. Typically, chemomechanical
planarization, known as CMP, is a nonhomogeneous
process and thickness variations can be
measured depending on the distance from a specific
die to the wafer center. These variations have an impact
on chip performances and thus on the final yield.
This effect may be amplified by the fact that thickness
variations on processed wafers introduce focus
issues during later photo-lithography steps. Original
chip layouts are modified by inserting dummies
to correct thickness variation issues due to CMP, but
these correction are based on models only depending
on average values. In this paper, we propose a
methodology to replace a single instance of the field
written on the mask by multiple instances of this field
as commonly used for Multi Layer Reticles. In the described
methodology, each field of a same mask does
not consist in different layers of the same chip, but of
an optimized image of the same layer of the chip.
With the emergence of submicron technologies new product development costs have soared to reach an average of
$15M. This includes all direct and indirect costs from specification to the start of volume production. At 65nm a single
mask set costs more than $1M. As statistically final silicon needs at least one rework on metal layers, we can roughly
estimate that mask budget is at least 10% of the chip development.
It is then obvious that IDM companies as well as fabless design centers must take special care for mask management.
Improving data exchange between mask data preparation teams and mask shops by using the SEMI-P10 standard has
been a great step, but building an internal mask data preparation database to warrant a safe traceability of all masks still
remains a challenge.
This paper describes a relational database, which manages all the data related to mask data preparation during the entire
life of the project. This database is not only dedicated to mask ordering, it also includes feedbacks on mask
manufacturing from the mask shop and on silicon manufacturing from the production line making mask traceability
possible.
The cost of production of a photomask set has been soaring over the last few years, and now reaches $1 million to $2
million, almost 10% of the overall cost of a new project development. And new projects have seen their profitability lifetime
reduced over time to 3 to 6 months. Any uncontrolled increase in cost or delay can make the difference between a
profitable or non profitable project, and can even lead to the cancellation of the entire project. For the last few years,
silicon manufacturability issues have been taken into account in the design process through a widespread use of Design
For Manufacturing tools, but so far the impact of design on mask manufacturability has not been thoroughly studied.
This article presents a novel Design For Mask Manufacturing approach, which defines a robust process encompassing
design rules and constraints, validation procedures, exchange mechanisms between all actors in the flow (designers,
mask shops, and foundry) in order to minimize the number and impact of mask design issues, to trace their root causes
and severity, and automation of the handoff of design and administrative data to the mask shop. A demonstrator for the
DFMM flow is being shown.
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