The 7nm node is the first generation where EUV lithography has been employed to replace a few multi-patterning immersion layers in high-volume manufacturing. The insertion of EUV lithography in the 7nm node can simplify the production process, reduce the cycle time, improve performance, and enhance yield. However, in order to fully take advantage of these benefits, we need to overcome new challenges introduced by EUV technology. In this paper, we present how to integrate 193nm immersion and EUV lithography in production and optimize the critical steps in the process. Our 7nm product was initially taped out with full 193nm-immersion masks. When the immersion process stabilized with a decent yield, we taped out n EUV layers to replace 3n immersion layers in the product. To migrate our production from the immersion process to the EUV process smoothly, we started a few Lots with splits of the immersion and the EUV processes. Some wafers went through the full immersion lithography process and the rest of the wafers went through the hybrid lithography process with about n layers using EUV. At the end, we compared the Si data of the two processes. After a few iterations of tweaking, the EUV process can provide better performance and higher yield than the immersion process. In this report, we also provide examples of how the better CD control with the EUV mask can be achieved, the Edge Placement Error (EPE) can be reduced and the uniformity of the EUV back-end-of-line (BEOL) layer can be improved during EUV process development.
After years of effort, extreme ultraviolet (EUV) lithography is finally in production for 7nm technology node and beyond. The 7nm node is the first generation where EUV has been employed to replace a few critical multi-patterning immersion layers in the product. While EUV lithography has helped to overcome some challenges in multi-patterning immersion lithography in advanced nodes such as process complexity and pattern uniformity, it has also brought about new challenges. In this paper, we choose the EUV contact layer as an example to describe how to insert EUV in a 7nm FPGA product to simplify the process and improve product performance. We select the EUV contact layer because it can improve the transistor performance by lowering the contact resistance with EUV’s reduced Edge Placement Error. We demonstrate how to tackle EUV contact defectivity, variability, and integration from a production point of view through the FPGA embedded memory CRAM. CRAM failure signatures and behaviors can be used to debug the contact related defects and monitor the contact resistance variation in the product. Combined with physical-failure-analysis (PFA) results on failed EUV contacts and CRAM characterization data, foundry can fine tune the EUV contact process to reduce contact defects and contact resistance variation. After a few iterations, our product achieves a stable and low-resistance EUV contact process with a significant reduction in contact failure rate.
Self-aligned double patterning (SADP) is being applied to 7nm technology node and below for back-end metal layers (routing layers) with pitches down to ~40nm. Unlike the traditional litho-etch-litho-etch (LELE) approach, SADP splits pitch using spacers whose 2nd pattern (Color-B) is self-aligned to its 1st pattern (Color-A). As a result, the SADP approach produces less variation than LELE approach by removing the second pattern misalignment on Si. Although SADP provides better overlay controllability than LELE, it still encounters many challenges. One of the challenges is controlling the 2nd patterning linewidth and uniformity. In general, the Color-B critical dimension (CD) has a larger variation than Color-A CD in the SADP process using Mandrel structure. In this paper, we investigate variations to the SADP Color-B CD based on self-aligned litho-etch litho-etch (SALELE) process flow, including the lithographic CD uniformity, hard mask etching, spacer etch and final Si etch. The corresponding contribution to Color-B CD variation is analyzed each step. After the major contributors to Color-B variation are identified, an experiment was designed to reduce Color-B pattern variation during the process. The silicon results show that compared with the old process condition, the new process can reduce Color-B variation significantly. With this new process, Color-B variation is comparable to Color-A variation.
As the semiconductor critical dimension (CD) is shrunk to 20nm node and beyond, double and triple patterning
technologies become necessary for current 193nm optical lithography. However, the new technologies induce a new
variation factor of the two or three mask pattern mismatching in terms of the wafer CD or alignment performance on
silicon. This mismatch can degrade matching circuit performance such as SRAM and analog circuit. In this paper, we
address the impact on our 20nm CRAM (configuration RAM used in FPGA circuit) performance caused by diffusion
layer pattern decomposition (coloring). Furthermore, we propose a methodology to optimize the coloring based on an
alignment performance assessment and CD control of two mask patterns printed on silicon wafer. In the same
experiment, we observed that the OPC (Optical Proximity Correction) is also critical to the coloring methodology. The
silicon results show that after the optimization, the impact of coloring-induced mismatch on CRAM performance can be
reduced significantly.
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