An interval-value based circuit simulation engine is proposed to estimate the transistor-level circuit performance
distribution without Monte-Carlo simulations. In the proposed flow, variability in process variables is first casted into an
interval representation; then an interval-valued circuit simulator, in which all real number operations are replaced by
interval operations, is used to simulate the circuit; the interval-valued simulation results can be used to extract
performance statistics. A runtime reduction over both Monte-Carlo simulation and response surface modeling has been
demonstrated, while excellent accuracies in transistor-level performance statistics are maintained. Future work includes
incorporating non-Gaussian distributions into the interval simulation, and adapting an interval-value based framework
into a design flow suitable for statistical performance optimization.
The growing impact of process variation on circuit performance requires statistical design approaches in which
circuits are designed and optimized subject to an estimated variation. Previous work [1] has explicitly accounted for
variation and spatial correlations by including extra margins in each of the gate delay and correlation factor between path
delays. However, as it is recently shown, what is often referred to as "spatial correlation" is an artifact of un-modeled
residuals after the decomposition of deterministic variation components across the wafer and across the die [2].
Consequently, a more accurate representation of process variability is to introduce these deterministic variability
components in the model, and therefore generate any apparent spatial correlation as the artifact of those deterministic
components, just like in the actual process. This approach is used to re-size an 8-bit Ladner-Fischer adder. The optimized
circuit delay distribution is obtained from Monte Carlo simulations. A layout generation tool is also being constructed to
incorporate the optimization procedure into the standard design flow. Custom circuit layouts are first subjected to design
rules to extract constraints that specify the margins allowed for each transistor active area edge movement. Sizing
optimization is then performed with design rule constraints taken into account. A new circuit layout is generated based
on the optimization results and checked to ensure DRC cleanness. The optimized layout can be subjected to further
verification such as hotspot detection to account for any additional layout dependant effects.
The growing impact of process variation on circuit performance requires statistical design approaches in which circuits
are designed and optimized subject to an estimated variation. Previous work [1] has shown that by including extra
margins in each of the gate delays and optimizing the gate sizes, the circuit delay variation can be reduced by half. Our
work goes further by deploying extended models that include delay variations due to Vth and Leff, as well as position
dependant variation. Two types of models have been proposed to account for various variations: 1) a model that
explicitly adds spatial correlation terms to the design objective; 2) a model that implicitly includes such effect through
the use of a modified version of Pelgrom's model. These design models are used to size a 32-bit Ladner-Fischer adder
and the circuit delay distributions are obtained from Monte Carlo simulations. The analysis shows that both types of
models have a noticeable performance improvements over the model presented in [1]. In addition, the second model
appears to be a more adequate method for modeling various variation components and has a better performance over the
first model; the drawback is a more complicated object function.
Circuit performance variability is significantly impacted by variations in gate length caused in microlithographic
pattern transfer [1]. Previous studies [2] have shown through simulation that by completely reconciling sources of
deterministic variation, long-range (millimeter separation scale) spatial correlation in the remaining variation is virtually
zero. To complete the model for spatial variation and correlation in critical dimension (CD), a new set of electrical
linewidth metrology (ELM) test structures were then designed to target the sub-mm regime [3]. In this work, we report
measurement results from those micron-scale ELM test structures. The micron-scale (0.2μm to 1.15mm) variation can be
decomposed into a very large chip-to-chip component, a small and systematic density-dependent component, and a small
random component; spatial correlation in gate length for the micron-scale regime is negligible.
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