With the improvement of chip debugging technology performance, the chip physical attack technology has also been developed rapidly. At present, the active shield has become the main protection against physical attacks on the chip. In this paper, for the shortcomings of digital shield detection circuit which cannot resist rewiring attack, we propose a scheme to collect some channel signal propagation delay to detect whether the shield is under rewiring attack on the basis of random code stream detection circuit. The scheme is applicable to parallel multi-channel shields. Random sequences is passed to the inner channels and pulse signals is passed to the outer channels, and the random sequence is compared in the detection circuit to determine whether the random sequence is consistent and the pulse signal width is within the error range, so as to determine whether the shield is damaged or modified. The final experiment shows that the scheme has the characteristics of simple digital type detection circuit, low overhead, after the implementation in smic0.18um process, the area of 25766um2, power consumption of 1.6639mw, can identify more than 8% of the shield failure area of rewiring attacks, to make up for the inherent parametric type detection circuit complexity defects.
Polynomial multiplication is the most compute-intensive in the Lattice-based post-quantum cryptography (PQC). This operation can be sped up using the number theoretic transform (NTT). A lot of research is currently being done on how to speed up the NTT algorithm. In light of these considerations, this study presents an NTT accelerator with a greatly simplified butterfly unit (BFU) architecture, a completely pipelined modular multiplication (MM) unit, and two parallel computing units. FPGA implementation is realized to evaluate this work. Through the experimental results, processing speed can achieve 2× improvements with controllable resource consumption.
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