As DRAM technology continues to evolve, advanced nodes shrink the device dimensions and raise the requirements for on-product overlay control to reduce residual error. Increased process complexity also demands tighter accuracy and robustness in metrology control, which necessitates new and innovative metrology enhancements and methods. Scatterometry-based overlay (SCOL®) metrology is a unique overlay metrology architecture that uses angle-resolved pupil imaging for overlay analysis and calculation. KLA’s SCOL metrology system offers wide-spectrum tunable laser and multi-wavelength (MWL) illumination patterns along with custom-designed advanced algorithms that provide multiple measurement conditions to meet unique layer and target requirements. This paper demonstrates improved overlay metrology accuracy and residual error on DRAM FEOL critical layer with SCOL technology. Multiwavelength and rotated quadrupole (RQ) illumination in the metrology tool are utilized to provide significantly improved residuals compared with the traditional single-wavelength (SWL) and on-axis illumination.
KEYWORDS: Overlay metrology, Semiconducting wafers, Advanced process control, Scanners, Scatterometry, Process control, Signal processing, Metrology, Control systems, Optical parametric oscillators
As the cell size of memory devices continues to shrink, tighter on-product overlay (OPO) specs require more accurate and robust overlay control. The overlay error budget mainly consists of the reticle, scanner, process, and metrology errors. The metrology budget is generally required to be <10% of the OPO control budget so that the accuracy and robustness of overlay metrology become more crucial as pattern size gets smaller on current 1x nm DRAM nodes. For overlay control in high-volume manufacturing (HVM), the primary optical overlay metrology typically used is Image-Based Overlay (IBO). In many cases, scatterometry overlay (SCOL), using a direct grating-scanning method, was shown to achieve more accurate After Development Inspection (ADI) overlay measurements. Using a tunable source and customized illumination pupil to directly scan within the grating cell, this technology improves accuracy by reducing the contribution of pattern surroundings in the scribe line, resulting in improved OPO control stability. Since the purpose of overlay control is to minimize actual device pattern misregistration, as measured after the etching process (AEI), achieving accurate and stable characterization of the systematic deviation between ADI and AEI overlay known as Non-Zero-Offset (NZO) is critically important. Accurate NZO applied to the scanner via the Advanced-Process-Control (APC) loop enables effective scanner overlay control at the post-lithography ADI step. This paper demonstrates a new scatterometry overlay technology adopted in DRAM use cases that resulted in OPO and NZO stability improvement. In addition, we demonstrate an efficient method to monitor HVM run-to-run overlay performance and NZO stability by comprehensive dataset modeling combining ADI and AEI.
As the semiconductor industry rapidly approaches the 3nm technology node, on product overlay (OPO) requirements have become even tighter and, as a result, reduction of residual overlay errors have become more important and challenging. Metrology performance enhancements are required to meet these demands. Using angle-resolved pupil imaging, Scatterometry Based Overlay (SCOL®) is a unique overlay metrology architecture that includes massive multi-signal analysis to enable improved accuracy and residuals reduction. In this paper we present a new Rotated Quadrupole (RQ) illumination pattern for SCOL metrology systems designed to enable broad measurable landscape coverage, support additional target design pitches with smaller target dimensions, and improve tool-to-tool matching (TTTM). These improvements enable the SCOL measurement system to provide higher measurement accuracy, reduce residuals error, and improve robustness to process variation. In this paper we will cover theory, some use cases, and measured results.
Semiconductor manufacturers are increasingly motivated to reduce overlay (OVL) target size. The scribe line area is in high demand, especially as width reduction efforts persist. Furthermore, since overlay control challenges require a higher sampling density, there is a growing need to place ultra-small targets inside the active chip, especially for devices with a large area. One of the main challenges of this new reality is producing smaller cell (grating) sizes to form smaller overlay targets, while maintaining compatible measurements to the standard target size of the same design. To overcome this challenge on typical scatterometry-based overlay (SCOL®) targets, we describe a method developed to perform the preliminary evaluation on a standard cell size of 8μm. This method selects a scalable setup by predicting performance on a 3-5um cell with the same target design (TD) parameters. This allows chipmakers to qualify the OVL measurement during process development on standard size targets, with the confidence that the optimized measurement conditions will be carried over to the smaller targets, saving time and real estate. However, even for scalable designs, target size reduction necessarily forces some size-performance tradeoffs: factors that are negligible for a standard target size can have significant impact on a scaled-down version of the same target design. In this paper we analyze these factors, show how they relate to measurement indicators, and present a method to apply such indicators toward setup selection. For each setup candidate this method can provide predicted performance and measurability as a function of cell size, a powerful tool for target area reduction.
A new algorithm called Single Wavelength Overlay Optimizer (SWOOP) enhances the performance of single-wavelength optical diffraction-based overlay metrology. SWOOP combines statistical learning with a physical model to advance the performance of single-wavelength measurements to that of multi-wavelength measurements. This is achieved by making a set of multi-wavelength measurements on the first wafer during a train phase and extracting the characteristic signature of the overlay inaccuracy at the pupil plane. This inaccuracy signature is then evaluated and removed in real time for single-wavelength measurements, resulting in improved accuracy and robustness to process variation without compromising throughput.
On Product Overlay (OPO) control is a critical factor in advanced semiconductor manufacturing. As feature sizes become smaller, OPO budgets become tighter, leaving less room for overlay (OVL) measurement inaccuracy. Over the last few years, overlay metrology’s focus has shifted inwards, towards accurate measurement conditions, as we aim to capture ever-smaller process and scanner variations. One method used to break down the OPO error budget is combining one or more accuracy flags and correlating them to various process impacts. Analyzing the overlay accuracy signature generated by accuracy flags can be useful for data validation, inspection and correlation to different processes and metrologies. In this paper, an extensive OVL accuracy experiment demonstrates the use of this new method. First, the method is applied to several wafers designed with intentional process variation, including variations in etch duration, Chemical Mechanical Polishing (CMP) duration, amorphous silicon (a-Si) thickness and titanium nitride (TiN) thickness. OVL results from the experimental wafers are compared with results from the reference (nominal) wafer.
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