Shrinkage of VLSI feature size and use of advanced Reticle Enhancement Technologies (RET) in manufacturing such as OPC and PSM have dramatically pushed up cost of mask. For example of a 130nm or 90nm mask set, the mask cost can easily reach one or two million US dollars. Shuttle mask is an effective method to share the mask cost by putting different chips on the same mask. Shuttle mask floorplanning is a key step to pack these chips according to certain objectives and constraints related to cost, yield, and manufacturability. In this paper, we present a simulated annealing based floorplanner to solve the shuttle mask floorplanning problem with multiple optimization objectives and constraints. We will consider area minimization, density optimization (for manufacturability enhancement with CMP), wafer utilization maximization, die-to-die inspection constraint, die orientation constraint and their combinations. A nice property of our floorplanner is that it can be easily adapted to different cost models of mask and wafer manufacturing. Experiments on industry data show promising results.
The cost of developing and deploying optical proximity correction (OPC) technology has become a non-negligible part of the total lithography cost of ownership (CoO). In this paper, we present our efforts to reduce costs associated with OPC in the development phase for the 90nm node, and production phase for the 130nm node.
The patterning of logic layouts for the 65nm and subsequent device generations will require the implementation of new capabilities in process control, optical proximity correction (OPC), resolution enhancement technique (RET) complexity, and lithography-design interactions. Many of the methods used to implement and verify these complex interactions can be described as design for manufacturability (DFM) techniques. In this paper we review a wide range of existing non-lithographic and lithographic DFM techniques in the semiconductor industry. We also analyze existing product designs for DFM technique implementation potential and propose new design methods for improving lithographic capability.
A shuttle mask has different chips on the same mask. The chips are not electrically connected. Alliance and foundry customers can utilize shuttle masks to share the rising cost of mask and wafer manufacturing. This paper studies the shuttle mask floorplan problem, which is formulated as a rectangle-packing problem with constraints of final die sawing strategy and die-to-die mask inspection. For our formulation, we offer a "merging" method that reduces the problem to an unconstrained slicing floorplan problem. Excellent results are obtained from the experiment with real industry data. We also study a "general" method and discuss the reason why it does not work very well.
In this paper, we discuss rule-based and model-based tiling methodologies for interconnect layers and their implications for design flows and performance. The addition of these 'dummy' tiling metal features modifies the final physical design and reduces the variation of back-end process parameters. This is a newly developing area of design flow and its importance is increasing with each succeeding semiconductor generation. Along with this development new methodologies and tools need to be introduced to handle time placement post-physical design, as well as efficient methods for representing the resulting large amount of dat. Additionally, the inclusion of tiles may introduce performance-degrading parasitic effects. The situation is complicated by the order of the elements of the design flow: parasitics characterization requires knowledge about the placement of dummy metal times, which takes place after physical design. In this study, we co pare the advantages of having uniform interconnect characteristics to the performance degradation caused by the additional layout parasitics. We also discuss several possible scenarios for the modification of design flows to account for these effects the thereby recover timing and power targets closure. These scenarios depend for their success on the very different length scales of polish and electromagnetic effects. Finally, an analysis of correlations in the parameters that define design corners leads to the new conclusion that the negative effect of increased parasitic loading due to tiling is not as sever as a simple analysis would suggest. This result is due to the fact that the tiling parasitic loading is somewhat compensated for by the improved planarity resulting from tiling, which tightens the process variation-induced spread of metal electrical parameters.
It is becoming increasingly clear that semiconductor manufacturers must rise to the challenge of extending optical microlithography beyond what is forecast by the current SIA roadmap. Capabilities must be developed that allow the use of conventional exposure methods beyond their designed capabilities. This is driven in part by the desire to keep up with the predictions of Moore's law. Additional motivation for implementing optical extension methods is provided by the need for workable alternatives in the event that manufacturing capable post-optical lithography is delayed beyond 2003. Major programs are in place at semiconductor manufacturers, development organization, and EDA software providers to continue optical microlithography far past what were once thought to be recognized limits. This paper details efforts undertaken by Motorola to produce functional high density silicon devices with sub-eighth micron transistor gates using DUV microlithography. The preferred enhancement technique discussed here utilizes complementary or dual-exposure trim-mask PSM which incorporates a combined exposure of both Levenson hard shifter and binary trim masks.
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