In this paper we present, for a CMOS n-diffusion photodiode, the effects of various doping concentrations on the
behaviour of two of the main parameters that characterize the performance of these devices: the photocurrent (for low
and for high levels of the illumination) and the dark current. We performed simulations aided by T-CAD tools for each
type of layer of the CMOS photodiode structure (substrate, p-epitaxial layer, n-diffusion layer) and evaluated the
behaviour of the photocurrent and dark current in various levels of the doping concentrations of these layers. These
results may be helpful in the process of fabricating these devices, where controlled amounts of impurities may be added to some layers (or their level might be reduced in some other layers), in order to maximize the photocurrent and to minimize the dark current in these structures.
Today, the CMOS image sensors are being used in an increasing number of applications. A significant
problem for these devices is due to the fact that the production testing is complicated and expensive. This
problem arises from the need to use light sources in order to test the photosensitive elements. As an
alternative solution, we proposed the use of a test performed in the absence of light. In order to evaluate the
quality of the proposed test approach, we performed an analysis of the defects and failure mechanisms in
the photodiode. This is the main contribution of the paper, as until now very little literature was written
concerning this subject, due to the fact that these defects are not well enough understood to enable the
development of a general model.
KEYWORDS: Monte Carlo methods, Phase measurement, Device simulation, Analog electronics, Picosecond phenomena, System on a chip, Telecommunications, Sensors, VHF band, Oscillators
This work deals with the development of test techniques for RF (Radio Frequency) components. The optimization of
production tests for RF PLLs (Phase Locked Loops) is targeted in particular. With devices of ever increasing speed, it is
no longer possible to measure some of the classical circuit performances even with dedicated RF testers. This problem
has been tackled in recent years by using BIST (Built-In Self Test) techniques for PLLs able to perform on-chip high
resolution measurements such as picosecond jitter. However, this risks to become also impossible at very high
frequencies.
This paper will present some preliminary work towards the optimization of production tests for RF PLLs with the aim of
avoiding traditional test measurements such as phase noise. Attention will be focused on single relevant blocks of the
RF PLL that have the greatest impact on phase noise and other critical performances. The VCO (Voltage Controlled
Oscillator) block will be first studied, since it gives the greatest contribution to phase noise. Our work will proceed by
taking into consideration the possibility to detect mismatches and leakages in CP (Charge Pump) currents that cause
spurious in the output spectrum. Simulation results in this paper will consider only catastrophic faults in circuit
components. The fault coverage of performances and simple test measurements that can be implemented on-chip for the
VCO is thus evaluated.
Oversampling Sigma-Delta modulators are commonly used in the design of high-resolution Analogue-to-Digital Converters (ADCs). The test of these ΣΔ modulators is a difficult and expensive task due to the need for the generation of a high-precision analogue test signal and the necessity of complex digital resources for the test response analysis. These problems can be overcome with the integration of the test in the chip by means of Built-In Self-Test (BIST) approaches. In this paper we present a BIST technique for high-precision ΣΔ modulators, by incorporating on-chip test signal generation and on-chip test response analysis capabilities. The approach, mostly digital, is based on the application of a binary stream as test stimulus and the re-use of the digital decimation filter present in a ΣΔ ADC for the test response analysis. The binary stimulus, which encodes a sinusoidal signal, is chosen to have a very high quality in the bandwidth of interest of the modulator. For the analysis of the test response, a high-precision sinusoidal signal is necessary as reference. This reference signal can be obtained from the same binary stimulus, by passing it directly to the digital decimation filter existing in the converter. Test response and sinusoidal reference signal are both compared by means of a sine-wave curve-fitting algorithm in order to obtain a measure of the SNDR (Signal-to-Noise-plus-Distortion Ratio). Simulation results show that this technique is capable of detecting the SNDR degradations caused by non-idealities in the modulator used in a 16-bit audio ΣΔ ADC architecture.
This paper describes the design, modeling and simulation of an acoustic microsystem in a pulse-echo ultrasonic application. The microsystem, used as emitter and receiver of ultrasonic signals, consists of a bulk micromachined suspended membrane. During emission, the membrane is placed in an oscillator loop and is thermally actuated at its resonance frequency (approximately equals 40 kHz). This frequency is slightly dependent on the membrane average temperature. The electronic interface circuit monitors this temperature. The membrane oscillations generate an ultrasonic signal (pulse) that propagates in the air and interacts with a solid body. As a result of this interaction, the ultrasonic signal is reflected on the solid surface and is received by the microsystem (echo). During reception, a piezoresistive bridge placed on the membrane is used for monitoring the membrane deflections. The resonance frequency of the membrane is tuned to the emitted frequency by keeping the membrane at the same temperature, achieving then maximum sensitivity. This paper presents in detail the behavioral modeling and simulation of the complete system. Some MEMS parts and the acoustic waves propagation are modeled using an Analogue Hardware Description Language (Verilog-A). The associated electronics are implemented in CMOS and the overall system is simulated with the SpectreHDL simulator in the CADENCE environment.
This paper describes a CMOS-compatible self-testable uncooled InfraRed (IR) imager that can be used in multiple applications such as overheating detection, night vision, and earth tracking for satellite positioning. The imager consists of an array of thermal pixels that sense an infrared radiation. Each pixel is implemented as a front-side bulk micromachined membrane suspended by four arms, each arm containing a thermopile made of Poly/Al thermocouples. The imager has a pixel self-test function that can be activated off-line in the field for validation and maintenance purposes, with an on-chip test signal generation that requires only slight modifications in the pixel design. The self-test of a pixel takes about 15 ms. The area overhead required by the test electronics does not imply any reduction of the pixel fill factor, since the electronics fits in the pixel silicon boundary. However, the additional self-test circuitry contributes to a small increase in the thermal conductance of a pixel due to the wiring of a heating resistor over the suspended arms. The self-test capability of the imager allows for a production test with a standard test equipment, without the need of special infrared sources and the associated optical equipment. A prototype with 8 X 8 pixels is currently in fabrication for validation of the self-test approach. In this prototype, each pixel occupies an area of 200 X 200 micrometer2, with a membrane size of 90 X 90 micrometer2 (fill factor of 0.2). Simulation results indicate a pixel thermal conductance of 22.6 (mu) W/K, giving a responsivity of 138 V/W, with a thermocouple Seebeck coefficient that has been measured at 248 (mu) V/K for the 0.6 micrometer CMOS technology used. The noise equivalent power (considering only Johnson noise in the thermopile) is calculated as 0.18 nW.H-1/2 with a detectivity of 5.03 X 107 cm.Hz1/2.W-1, in line with current state-of-the-art. Since the imager may need to measure irradiation intensities below 1(mu) W, with a pixel output voltage much smaller than 1 mV, the analog front-end electronics incorporated on the chip uses modulation and correlated-double-sampling to reduce the amplifier offset and the noise floor.
Suspended thermal MEMS is one of the major domains of application of CMOS-compatible bulk-micro machining technologies. In some applications, a tradeoff much be reached between the mechanical strength of the micro structure and the thermal losses through the support beams. This paper illustrates how suspended MEMS can be strengthened by means of additional support beams which have a very high thermal impedance, thus having a very small impact in the thermal behavior of the micro structure. A high thermal impedance beam can be considered as a new MEMS design cell. The use of this cell in the design of an electro thermal converter with long time constant is illustrated.
This paper describes an approach to fault simulation of MEMS using an analog Hardware Description Language (HDL). HDL languages facilitate the description of mixed-domain devices, providing powerful representation capabilities which are not limited to the use of the traditional equivalent electrical modes. This is exploited in this paper for fault simulation of MEMS, showing the advantages of using an HDL for this task. An electro-thermal converter is used as test vehicle, for which an equivalent electrical more is readily obtained. Typical defects and failure mechanisms which can affect these devices fabricated using CMOS-compatible bulk micromachining are shown. These defects are used for illustrating the fault simulation approach which appears to be more comprehensive and systematic than previous approaches.
The work described in this paper is aimed at fault modeling and fault simulation of electrostatic comb-drives. At present, we have taken into account the most typical defects which we have encountered through fabrication of resonator test structures. These defects include stiction of the suspended beams to the substrate surface and the break of comb-drive model, and the impact of a faulty comb-drive is assessed for different resonator-based designs.
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