Improving local critical dimension uniformity (LCDU) as well as productivity in the extreme pitch of EUV layers is the most important challenge in DRAM device. In general, automated source optimization (SO) process is limited to investigate all possible candidates for the best LCDU performance, like fixing the amount of mirror in specific sigma and generating uncommon pole shapes. In this paper, we present LCDU improvement method in hexagonal contact array patterns based on controlling the center sigma position in the EUV pupil. We demonstrated that the LCDU was improved when the source points were located on the outer edge side of pupils regardless of normalized image log slope (NILS). This indicated the mirror location in the source is significant for LCDU in the similar NILS conditions. Moreover, it was confirmed that the CD along the critical direction increased as source points moved toward the center of the 3-beam imaging area, thus the changed CD ellipticity could further improve LCDU or cut down ACI defect source. The results showed a similar tendency in both the binary mask (BIN) and phase shift mask (PSM) even to differ type of resist. Overall, we verified the correlation of LCDU and ADI CD ellipticity through the sigma center position control, and we believe this approach will contribute to future research on improving LCDU.
Accurate prediction of resist profile has become more important as technology node shrinks. Non-ideal resist profiles due to low image contrast and small depth of focus affect etch resistance and post-etch result. Therefore, accurate prediction of resist profile is important in lithographic hotspot verification. Standard approaches based on a single- or multiple-2D image simulation are not accurate, and rigorous resist simulation is too time consuming to apply to full-chip. We propose a new approach of resist profile modeling through machine learning (ML) technique. A position of interest are characterized by some geometric and optical parameters extracted from surroundings near the position. The parameters are then submitted to an artificial neural network (ANN) that outputs predicted value of resist height. The new resist 3D model is implemented in commercial OPC tool and demonstrated using 10nm technology metal layer.
Accurate prediction of etch bias has become more important as technology node shrinks. A simulation is not feasible solution in full chip level due to excessive runtime, so etch proximity correction (EPC) often relies on empirically obtained rules or models. However, simple rules alone cannot accurately correct various pattern shapes, and a few empirical parameters in model-based EPC is still not enough to achieve satisfactory OCV. We propose a new approach of etch bias modeling through machine learning (ML) technique. A segment of interest (and its surroundings) are characterized by some geometric and optical parameters, which are received by an artificial neural network (ANN), which then outputs predicted etch bias of the segment. The ANN is used as our etch bias model for new EPC, which we propose in this paper. The new etch bias model and EPC are implemented in commercial OPC tool and demonstrated using 20nm technology DRAM gate layer.
With shrinking feature size, runtime has become a limitation of model-based OPC (MB-OPC). A few machine learning-guided OPC (ML-OPC) have been studied as candidates for next-generation OPC, but they all employ too many parameters (e.g. local densities), which set their own limitations. We propose to use basis functions of polar Fourier transform (PFT) as parameters of ML-OPC. Since PFT functions are orthogonal each other and well reflect light phenomena, the number of parameters can significantly be reduced without loss of OPC accuracy. Experiments demonstrate that our new ML-OPC achieves 80% reduction in OPC time and 35% reduction in the error of predicted mask bias when compared to conventional ML-OPC.
Verification of full-chip DSA guide patterns (GPs) through simulations is not practical due to long runtime. We develop a decision function (or functions), which receives n geometry parameters of a GP as inputs and predicts whether the GP faithfully produces desired contacts (good) or not (bad). We take a few sample GPs to construct the function; DSA simulations are performed for each GP to decide whether it is good or bad, and the decision is marked in n-dimensional space. The hyper-plane that separates good marks and bad marks in that space is determined through machine learning process, and corresponds to our decision function. We try a single global function that can be applied to any GP types, and a series of functions in which each function is customized for different GP type; they are then compared and assessed in 10nm technology.
Comprehensive and compact test patterns are crucial to the development of new semiconductor
technology. In particular, the random nature of routing layers tends to create many hotspots, corresponding to patterns which are difficult to predict. Conventional group of test patterns consists of parametric typical patterns and real layout clips, which contain a lot of redundancy. The paper addresses a problem of generating comprehensive yet compact group of test patterns for random routing layers. A new method of pattern extraction and classification is proposed to solve the problem.
More complex source and mask shapes are required to maximize the process window in low κ1 era. In simulation, the improvement can be shown well with ideal source and mask shapes. However imperfection of the source and mask can cause critical dimension (CD) errors and results in smaller process margin than expected one. In this paper, it is shown
that how process margins can be improved with different source and mask complexities. Also the effect of source and
mask complexities on CD errors and process margin degradation is discussed. The error source of the electron beam
mask pattern generator is investigated and used for mask CD uniformity estimation with different mask complexity.
Model-based Optical Proximity Correction (OPC) is widely used in advanced lithography processes. The OPC model
contains an empirical part, which is calibrated by fitting the model with data from test patterns. Therefore, the success of
the OPC model strongly relies on a test pattern sampling method.
This paper presents a new automatic sampling method for OPC model calibration, using centroid-based clustering in a
hybrid space: the direct sum of geometrical sensitivity space and image parameter space. This approach is applied to an
example system in order to investigate the minimum size of a sampling set, so that the resulting calibrated model has the
error comparable to that of the model built with a larger sampling set.
The proposed sampling algorithm is verified for the case of a contact layer of the most recent logic device.
Particularly, test patterns with both 1D and 2D geometries are automatically sampled from the layer and then measured
at the wafer level. The subsequent model built using this set of test patterns provides high prediction accuracy.
KEYWORDS: Optical proximity correction, Lithography, Signal processing, Image quality, Nanoimprint lithography, Photomasks, Calibration, System on a chip, Data modeling, Computer simulations
In this paper, we introduce a rigorous OPC technology that links the physical lithography simulation with the OPC. Firstly, the various aspects of the rigorous OPC, related to process flow, are discussed and the practical feasibility of the embedded rigorous verification is taken into account, which can make the rigorous treatment of the full-chip level possible without any additional manual efforts. We explain an embedded rigorous verification flow and the basic structure of its functionality. Finally, its practical application to real cases is discussed.
This paper presents an effective methodology for etch PPC (Process Proximity Correction) of 20 nm node
DRAM (Dynamic Random Access Memory) gate transistor. As devices shrinks, OCV(On chip CD Variation)
control become more important to meet the performance goal for high speed in DRAM. The main factors which
influence OCV are mask, photo, etch PPE (Process proximity effect) in DRAM gate. Model based etch PPC is
required to properly correct Etch PPE as device density increases. To improve OCV in DRAM gate, we applied
new type of etch loading kernel. It is called Vkernel which accounts for directional weight from the point of
interest. And we optimized the etch PPC convergence by optimizing the etch PPC iteration. Because of density
difference between spider mask and real gate mask, the skew difference occurs between them. We tested the
effect of long range density using same real gate pattern clip by varying mask open image size from 0.5 ~ 10
mm. The ADI CD difference was on average in the order on 2 nm for varying mask open image size. But the
ACI CD difference (the average of CD range by varying open image size) was very noticeable (about 15 nm).
This result shows that etch skew affected by long range density by mm unit size. Due to asymmetrical pattern in
real gate mask, spider mask which have symmetrical patterns is necessarily used to make PPC model. The etch
skew of real pattern clip in spider mask was not also the same for the real pattern in real gate mask. To reduce
this skew difference between spider mask and real mask, we applied open field mask correction term and long
range density effects correlation equation to PPC modeling. There was noticeable improvement in the accuracy
of PPC model. By applying these improvement items, OCV of 20 nm node DRAM gate is shown to improve up
to 67%.
Generally speaking, the models used in the optical proximity effect correction (OPC) can be divided into three parts,
mask part, optic part, and resist part. For the excellent quality of the OPC model, each part has to be described by the
first principles. However, OPC model can't take the all of the principles since it should cover the full chip level
calculation during the correction. Moreover, the calculation has to be done iteratively during the correction until the cost
function we want to minimize converges. Normally the optic part in OPC model is described with the sum of coherent
system (SOCS[1]) method. Thanks to this method we can calculate the aerial image so fast without the significant loss of
accuracy. As for the resist part, the first principle is too complex to implement in detail, so it is normally expressed in a
simple way, such as the approximation of the first principles, and the linear combinations of factors which is highly
correlated with the chemistries in the resist. The quality of this kind of the resist model depends on how well we train the
model through fitting to the empirical data. The most popular way of making the mask function is based on the
Kirchhoff's thin mask approximation. This method works well when the feature size on the mask is sufficiently large,
but as the line width of the semiconductor circuit becomes smaller, this method causes significant error due to the mask
topography effect. To consider the mask topography effect accurately, we have to use rigorous methods of calculating
the mask function, such as finite difference time domain (FDTD[2]) and rigorous coupled-wave analysis (RCWA[3]). But
these methods are too time-consuming to be used as a part of the OPC model. Until now many alternatives have been
suggested as the efficient way of considering the mask topography effect. Among them we focused on the boundary
layer model (BLM) in this paper. We mainly investigated the way of optimization of the parameters for the BLM since
the feasibility of the BLM has been investigated in many papers[4][5][6]. Instead of fitting the parameters to the wafer
critical dimensions (CD) directly, we tried to use the aerial image (AI) from the rigorous simulator with the
electromagnetic field (EMF) solver. Usually that kind of method is known as the staged modeling method. To see the
advantages of this method we conducted several experiments and observed the results comparing the method of fitting to
the wafer CD directly. Through the tests we could observe some remarkable results and confirmed that the staged
modeling had better performance in many ways.
As the design node gets smaller, using the aggressive mask optimization becomes indispensable emerging technology.
However, during the aggressive optimization, we have frequently met problems that the optimized feature size gets
smaller as Mask manufacturing Rule Checking (MRC) limitation. In this case, process window cannot improve more.
Moreover, mask drawing error could be significant when the optimized main feature is as small as MRC limitation. As a
solution for this problem, we have generally tried to develop the advanced mask manufacturing process. However,
nowadays, it is truly not easy to improve the mask resolution.
In this study, we found out the fact that the current MRC parameters are not good enough to reflect the mask patterning
limitation. Thus, many small patterns have been eliminated by the MRC during the optimization, even though the
patterns could be drawn well on the mask. In this paper, we suggest more effective MRC parameter; area based MRC.
We introduce the evaluation result that represents the actual coverage of MRC. It proves that the area based MRC can
reflect the mask process limitation much better than current MRC. Finally it is shown that the effect and utility of the
area based MRC on the practical case by using inverse lithography technology (ILT).
SRAF (sub-resolution assist feature) generation technology has been a popular resolution enhancement technique in
photo-lithography past sub-65nm node. It helps to increase the process window, and these are some times called
ILT(inverse lithography technology). Also, many studies have been presented on how to determine the best positions of
SRAFs, and optimize its size. According to these reports, the generation of SRAF can be formulated as a constrained
optimization problem. The constraints are the side lobe suppression and allowable minimum feature size or MRC (mask
manufacturing rule check). As we know, bigger SRAF gives better contribution to main feature but susceptible to SRAF
side lobe issue. Thus, we finally have no choice but to trade-off the advantages of the ideally optimized mask that
contains very complicated SRAF patterns to the layout that has been MRC imposed applied to it. The above dilemma can
be resolved by simultaneously using lower dose (high threshold) and cleaning up by smaller MRC. This solution makes
the room between threshold (side lobe limitation) and MRC constraint (minimum feature limitation) wider. In order to
use smaller MRC restriction without considering the mask writing and inspection issue, it is also appropriate to identify
the exact mask writing limitation and find the smart mask constraints that well reflect the mask manufacturability and the
e-beam lithography characteristics.
In this article, we discuss two main topics on mask optimizations with SRAF. The first topic is on the experimental work
to find what behavior of the mask writing ability is in term of several MRC parameters, and we propose more effective
MRC constraint for aggressive generation of SRAF. The next topic is on finding the optimum MRC condition in
practical case, 3X nm node DRAM contact layer. In fact, it is not easy to encompass the mask writing capability for very
complicate real SRAF pattern by using the current MRC constraint based on the only width and space restriction. The
test mask for this experimental work includes not only typical split patterns but also real device patterns that are
generated by in-house model-based assist feature generation tool. We analyzed the mask writing result for typical
patterns and compared the simulation result, and wafer result for real device patterns.
Recently, there have been many studies on the mask topography effect on patterning. Most of existing papers report
generally focused on the difference of the aerial image between the thin mask approximation and the rigorous
topographic mask models. In this paper, the mask topography effect was analyzed from an OPC modeling perspective.
We compared the accuracy of two types of the virtual OPC model of contact patterns that one model used the virtual test
patterns generated by the lithography simulator based on the thin mask approximation model and the virtual test patterns
of another model were made by the rigorous topographic mask simulation based on FDTD (Finite Difference Time
Domain) method. All conditions of lithography simulations and OPC modeling between two models were same except
the mask topography parameters in generating virtual test patterns. Differences in model accuracy and convergence
values of regression parameters of each models indicated that current OPC modeling tool based on the thin mask
approximated optical simulation did not sufficiently cover the mask topography effect, and 3D mask effect should be
considered more carefully.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.