Lithography development has become extremely computationally intensive. For a particular technology node
being developed, it is critical to determine the optimum source and OPC/RET for each layer. In this paper we
present a flexible new computation system for automation of source, OPC and RET optimization of advanced lithography layers. Of course, before determining the optimum source/RET/OPC of any layer, it is equally critical to determine the design rules which can be manufactured at a particular technology node. The design rule computational lithography problem is a superset of the source/OPC/RET optimization problem. With an automated methodology, time for process development can be reduced dramatically if a process development engineer can determine the design rules through accurate, automated simulation of the entire flow.
At advanced technology nodes with extremely low k1 lithography, it is very hard to achieve image fidelity requirements and process window for some layout configurations. Quite often these layouts are within simple design rule constraints for a given technology node. It is important to have these layouts included during early RET flow development. Most of RET developments are based on shrunk layout from the previous technology node, which is possibly not good enough. A better methodology in creating test layout is required for optical proximity correction (OPC) recipe and assists feature development.
In this paper we demonstrate the application of programmable test layouts in RET development. Layout pattern libraries are developed and embedded in a layout tool (ICWB). Assessment gauges are generated together with patterns for quick correction accuracy assessment. Several groups of test pattern libraries have been developed based on learning from product patterns and a layout DOE approach. The interaction between layout patterns and OPC recipe has been studied.
Correction of a contact layer is quite challenge because of poor convergence and low process window. We developed test pattern library with many different contact configurations. Different OPC schemes are studied on these test layouts. The worst process window patterns are pinpointed for a given illumination condition.
Assist features (AF) are frequently placed according to pre-determined rules to improve lithography process window. These rules are usually derived from lithographic models and experiments. Direct validation of AF rules is required at development phase. We use the test layout approach to determine rules in order to eliminate AF printability problem.
Semiconductor manufacturers spend hundreds of millions of dollars and years of development time to create a new
manufacturing process and to design frontrunner products to work on the new process. A considerable percentage of this
large investment is aimed at producing the process design rules and related lithography technology to pattern the new
products successfully. Significant additional cost and time is needed in both process and design development if the
design rules or lithography strategy must be modified. Therefore, early and accurate prediction of both process design
rules and lithography options is necessary for minimizing cost and timing in semiconductor development.
This paper describes a methodology to determine the optimum design rules and lithography conditions with high
accuracy early in the development lifecycle. We present results from the 32nm logic node but the methodology can be
extended to the 22nm node or any other node. This work involves: automated generation of extended realistic logic test
layouts utilizing programmed teststructures for a variety of design rules; determining a range of optical illumination and
process conditions to test for each critical design layer; using these illumination conditions to create a extrapolatable
process window OPC model which is matched to rigorous TCAD lithography focus-exposure full chemically amplified
resist models; creating reticle enhancement technique (RET) recipes which are flexible enough to be used over a variety
of design rule and illumination conditions; OPC recipes which are flexible enough to be used over a variety of design
rule and illumination conditions; and OPC verification to find, categorize and report all patterning issues found in the
different design and illumination variations. In this work we describe in detail the individual steps in the methodology,
and provide results of its use for 32nm node design rule and process optimization.
Production optical proximity correction (OPC) tools employ compact optical models in order to accurately
predict complicated optical lithography systems with good theoretical accuracy. Theoretical accuracy is
not the same as usable prediction accuracy in a real lithographic imaging system. Real lithographic
systems have deviations from ideal behavior in the process, illumination, projection and mechanical
systems as well as in metrology. The deviations from the ideal are small but non-negligible. For this study
we use realistic process variations and scanner values to perform a detailed study of useful OPC model
accuracy vs. the variation from ideal behavior and vs. theoretical OPC accuracy. The study is performed
for different 32nm lithographic processes. The results clearly show that incorporating realistic process,
metrology and imaging tool signatures is significantly more important to predictive accuracy than small
improvements in theoretical accuracy.
Through the use of an optimized 248 nm optical lithography process and an in-situ resist trimming step developed as part of the gate layer etch, we have been able to fabricate 0.12 micron logic gates with acceptable manufacturing process latitudes. The resist trimming step is performed just prior to etching the SiON anti-reflective coating layer. Because the trimming step is done in-situ as part of the gate etch process, the impact on throughput is minimal. The resist trimming process allows the printing of features larger than the target width, increasing the photolithography process latitude by allowing the process to be run at the most optimal conditions. The trimming step also reduces the line edge roughness which is commonly seen for many chemically amplified photoresists. Photolithography process latitudes with and without trimming are compared for on-wafer dimensions of 0.15 and 0.12 micron. The effect of the trimming step on intrawafer critical dimension control is quantified, and electrical performance of the transistors is presented. The extendibility of this technique for 0.10 micron features is presented. Empirical results are compared to PROLITH simulations, and results of a feasibility study for 193 nm lithography are included.
One of the biggest challenges for printing 0.6 micrometers metal lines (1.3 micrometers pitch) over 1.1 micrometers of topography is the shallow depth of focus. Total random errors, or, Built In Focus Errors (BIFE) for the class of steppers used in this study was determined to be 0.48 micrometers . When topography, and field curvature/astigmatism, are factored in, the required depth of focus to print the metal lines is approximately 2.18 micrometers . However, the 'Available' DOF (as determined from PROLITH simulations) is only 1.8 micrometers . The deficit between available DOF and required DOF grows bigger when there are multiple steppers. To overcome this deficiency, various techniques have been studied. Topography reduction by 0.4 micrometers was achieved by the use of Reverse Well technology. Effect of different resist chemistries, off-axis illumination, variation in numerical aperture and partial coherence, on the focus latitude are shown.
This paper discusses two lithography strategies for printing 0.35 micrometers features: broad band deep ultraviolet (DUV) lithography using a chemically amplified resist dyed to an optical density of 0.40 per micrometers and the use of high numerical aperture (NA) i-line lithography with an advanced i-line resist. Lithographic results such as linearity, exposure and focus latitudes, reflective notching control, and post exposure bake (PEB) delay time are compared. Results on product wafers are also illustrated. Finally, experimental data is compared with PROLITH/2 simulations.
In this work critical dimension (CD) and site focal plane deviation (SFPD) measurements were made on a patterned resist test structure with 0.8 micron dense lines with a pitch of 1.6 micrometers . The CD and SFPD were tracked through all critical wafer processing steps. The range in SFPD was negligible throughout front end processing, with average SFPDs less than 0.25 microns. Significant increase in the mean and variance of SFPD was observed at later process modules. An increase in the SFPD directly reduces the focus budget, resulting in an increase in the variation of the CD across a field as well as a degradation of the resist profile. Within-field CD variation (3 sigma) for a SFPD of 0.05 micrometers was observed to be less than 0.03 micrometers (30 measurement sites within a field) whereas the three sigma CD variation for a SFPD of 3.8 micrometers was observed to be 0.45 micrometers . Two-dimensional and 3-D graphical correlations are presented, and the use of the SFPD/CD correlation technique to photolithographic process optimization is discussed.
It is becoming increasingly clear that DUV excimer laser based imaging will be one of the technologies for printing sub-half micron devices. This paper reports the investigation of 0.35 micrometers photolithography process using chemically amplified DUV resists on organic anti- reflective coating (ARC). Production data from the GCA XLS excimer DUV tools with nominal gate width of 0.35 micrometers lines, 0.45 micrometers spaces was studied to demonstrate device production worthiness. This data included electrical yield information for device characterization. Exposure overlay was done by mixing and matching DUV and I-line GCA steppers for critical and non critical levels respectively. Working isolated transistors down to 0.2 micrometers have been demonstrated.
This paper examines the effects of specular and diffuse reflectivities, both empirically and theoretically, on the imaging process for highly reflective substrates. Aluminum (Al) and Titanium Nitride (TiN) wafers were used extensively in this study. TiN wafers were prepared with varying specular reflectivities and virtually no diffuse reflectivity. Dose to clear on TiN wafers was found to increase linearly with specular reflectivity in the absence of any diffuse component. Aluminum wafers were prepared with high specular reflectivity and varying diffuse reflectivities. On these Al wafers, the increase in diffuse reflectivity decreased the dose to clear in a nonlinear fashion. A theoretical explanation for the observed phenomenon is presented based on the interaction of thin film interference effects with diffuse scattering. Modelling results based on this theory are shown to be in good agreement with the experimentally observed data. Based on these results, a method for the generation of specification limits for the allowable variations in specular and diffuse reflectivities are also presented. Also discussed are the tools and methods used for measuring substrate reflectivity to obtain these specification limits.
Contact structures represent some of the most challenging features to image using deep UV excimer laser lithography. A single resist process, exposure dose, and focal setting must compensate not only for variations in the reflectivities of gate (Le, polysilicon) and diffusion (i.e., oxide) substrates, but must deal with variations in underlying topographical features which create a non-uniform resist film over a non-planar imaging surface. Commercially available deep UV photoresists are negative toned, requiring the use of clear field photomasks for imaging of submicron contact structures. In this paper, we describe three strategies for enhancing the ability to image contact structures using currently available negative toned chemically amplified deep UV photoresists: (1) optimization of central exposing laser wavelength, (2) incorporation of anti-reflective coatings, and (3) optimization of resist film thickness for sidewall profile enhancement. These approaches should also enhance imaging of contacts using positive tone photoresists, once they are commercially available
The development of tools and processes for a stable patterning process must successfully integrate the lithography and etch modules into a workable unit. As lithography becomes increasingly complex, such as in the case of excimer laser DUV photolithography, the link between the two processing steps becomes even more critical.
This work characterized some of the challenges of integrating a DUV lithography process with the standard etching modules. The process studied utilized a negative acting
photoresist and a spin-on Anti Reflection Coating. Pattern transfer processes were characterized in terms of critical dimension control, contamination concerns and critical dimension repeatability. Further, the effect of critical lithography parameters were examined as to their modulation of post etch profile characteristics and the effect on focus latitude.
This paper discusses issues concerning the use of a thin absorbing organic anti-reflective (AR) coating for 0.5 micrometers excimer laser lithography. Linewidth profiles, CD control, substrate dependence and etching are all affected by the presence of the AR coating. The advantages of implementing highly absorbing organic AR coatings are that CD control with resist thickness (swing curve) is improved, substrate reflectivity effects becomes negligible, adhesion is improved and reflective notching is decreased, leading to better CD control over topography. For example, the swing curve was reduced from 0.18 micrometers to 0.04 micrometers by using an absorbing AR film. Exposure/focus latitudes were modeled using Obelisk software. This gave an exposure dose of 26 mJ/cm2 for printing 0.5 micrometers dense lines on aluminum, poly- silicon, oxide, nitride and tungsten. In addition, the exposure latitudes for these substrates was found to be +/- 10% when the total depth of focus was 1.2 micrometers . Statistically designed experiments were used to optimize resist profiles of the SNR248 resist images on AR coating. Issues relating to implementing organic AR coatings under a 1300 angstrom absorbing AR coating reduced reflectivity variation on poly-silicon from 38% to 6% over a resist thickness range of 350 angstrom. By using the AR coating the swing curve variation was reduced from 0.18 micrometers to 0.04 micrometers .
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