Etching process is an indispensable patterning step in semiconductor device manufacturing. The etch bias compensation is critical in optical proximity correction (OPC) to ensure lithography fidelity and device performance. Therefore, accurate prediction of etch bias has become more crucial as moving to advanced technology node etching process. This study aims to develop an etch bias prediction model based on ensemble learning, specifically utilizing the Random Forest algorithm. A substantial simulation results comprising linewidth, pitch, and corresponding etch bias data for one-dimensional layouts was collected. Subsequently, we employed the Random Forest algorithm, a powerful ensemble learning method, to construct the etch bias prediction model. Random Forest effectively captures the intricate relationships between linewidth, pitch, and etch bias by combining multiple decision trees. Finally, we utilized transfer learning techniques to fine-tune a pre-trained random forest model using real experimental data, resulting in the final model. Compared to traditional machine learning methods, such as the BP neural network, this approach features with faster training speed and better robustness, the Random Forest model exhibits stronger transferability across different technology nodes and different process conditions.
Atomic layer deposition (ALD) technology is a self-limiting film deposition process that grows films on substrates through repeated process cycles of precursor dosing, purge, co-reactant dosing and purge. This technology is widely utilized in advanced technology node processes due to its merits of excellent step coverage and atomic scale film thickness control. However, as the industry moves to three-dimensional (3D) device architectures, ALD faces emerging challenges such as the bottle neck phenomenon in extremely high aspect ratio structure with nanometer scale trench or hole open. ALD modeling provides insights into the underlying mechanisms and help engineers optimize the process. There has been research on different kind of ALD process models on film conformity, growth profile and saturation behavior at multiscale from reactor to micro-feature and molecular level. Angel Yanguas-Gil et al. proposed a reactor scale model which discussed the ideal and non-ideal self-limited processes in a cylindrical and a 300 mm wafer cross-flow reactor. Adomaitis et al. presented a multiscale model to describe the reactant transport in a high aspect ratio nanopore and growth of ALD film based on continuum and Monte Carlo model. In this work, we propose an ALD model in order to simulate the spatial ALD process, coupling with surface reaction kinetics theory and hydrodynamics model. Firstly, we analyze and model the adsorption process of precursor molecules and co-reactant molecules, as well as their transport mechanism in ALD reactor chamber. Secondly, we discuss how the substrate temperature, precursor and co-reactant partial pressure, and reaction probabilities influence coverage distribution and growth per cycle in spatial ALD process. This model enables the possibility of spatial ALD process parameter optimization in an efficient and economy way.
In gate-all-around nanosheet (GAA-NS) transistor manufacturing, the SiGe layer plays an important role as a sacrificial layer, requiring precisely controlled and highly selective isotropic etching. In our previous work, we proposed a novel isotropic selective quasi-atomic layer etching (quasi-ALE) method based on O2 plasma self-limiting oxidation and CF4/C4F8 self-limiting selective etching. A vertical nanowire transistor with a diameter less than 20nm and an accuracy error less than 0.3nm has been developed. In this paper, we adopt this method to cavity etching of horizontally stacked nanosheets, using an ICP source to perform self-limiting oxidation of the SiGe layer followed by self-limiting selective removal of oxide (a two-step self-limiting cycle) to form inner spacer cavity. Experimental results show that compared with the strong dependence of the etching amount on SiGe thickness and Ge composition in traditional ICP dry etching, the quasi-ALE technology tends to weaken this size and concentration loading effect due to the self-limiting of each cycle reaction. In addition, we also demonstrated the latest progress in corresponding ALE simulation using a commercial feature-scale plasma process simulator named PEGASUS. The simulation results show that the SiGe etching amount per cycle (EPC) is about 0.3nm, which is basically consistent with the experimental results. This quasi-ALE method demonstrates promising performance for preparing GAA device channels, nanosensors, and other application in future.
Bowing is one of plasma etching effects that negatively impact device performance. Although there has been plenty of research work on micro-feature surface etch modeling to investigate bowing effect, limited research has been reported on the influence of hardmask morphology on bowing effect. In this paper, we present a plasma etching model based on Monte Carlo simulation with cellular method in order to simulate the feature profile evolution of etching process in nano-scale. The relationship among hardmask angle, open CD and distribution of reflected ion flux on the sidewall from the opposite hardmask was calculated. The reflected ion flux was heavily concentrated in the upper part of the sidewall in the case of a tapered hardmask, and this was the main mechanism of the bowing formation. This model considers chemical reactions and a novel particle reflection algorithm which is a prominent mechanism. This model is capable of reproducing the feature in periodic dense trenches with dimension of tens of nanometers. The hardmask morphology considered in our study includes hardmask angle (θ) and pattern (CD and pitch). As the hardmask angle decreases, the bowing becomes severe, when CD equals to 90nm and θ equals to 70°, the bowing deviation (D=(W-CD)/2) and relative deviation (Δ D=D/CD×100 %) are 23.86nm (26.51 %). In contrast, as the CD increases, the bowing becomes slight. However, bowing moves toward the bottom of the hole as the CD increases. When CD equals to 150nm and θ equals to 70°, the bowing deviation is 18.95nm (12.63 %). Accordingly, a vertical hardmask is very important for a small CD trench.
Three-dimensional (3D) architectures have become main stream for the advanced node logic and memory devices, such as the gate-all-around field effect transistors (GAAFET) and 3D dynamic random access memory (3D DRAM). These devices feature with stacked structure offers higher integration, better device performance and lower power consumption. However, the manufacturing of such devices needs high aspect ratio (AR) feature processing which brings challenges to conventional thin film deposition process such as chemical vapor deposition (CVD). SiN is a common barrier and spacer material and usually grown by CVD with a gas mixture of SiH4/NH3/N2. In this work, we conduct simulations of SiN CVD process in deep trenches to investigate the thin film step coverage dependence on process conditions and AR. We adopt the reaction-diffusion theory to develop the surface growth model of SiN deposition and set a few semi-empirical mechanism parameters to calibrate the model with experimental results. Simulation results show that in the substrate trench with 50nm open CD and AR of 5, the film deposition step coverage becomes better as the fluxes of neutrals increases, corresponding to lager fneu value. Simulations also suggest that with trench depth fixed at 250nm, as the AR of the trench increases, the overall deposition rate in the trench decreases. As the AR increases, the density of the reactant species such as radicals and ions decrease and the diffusion-limited phenomenon appear, which further reduces the reaction rate at the bottom of the trench.
The lateral gate-all-around (GAA) field effect transistor is considered to be the most promising candidate for the next generation of logic devices at the 3nm technology node and beyond. SiGe plays an important role as a sacrificial layer in the GAA device, which requires isotropic etching, and the quality of the etching has a critical impact on the device performance. However, there is no definite scheme in the industry for the choice of etching method. In this paper, we choose two etching methods: CP(Inductively coupled Plasma) and RPS (Remote Plasma Source) etching according to the presence or absence of particle incidence. The profile and etching effect of the two etching methods are analyzed by PEGASUS simulation software. The presence or absence of particle incidence has different effects on the damage of the structure, the inconsistency of etching amount and the reflection of the particles on the Si surface. Compared with ICP etching, the optimization of RPS etching on etching damage and etch amount consistency is verified by TEM and roughness characterization . And through the extraction of MOSCAP capacitance, it is found that the density of interface states(Dit) after ICP etching is 3.5 times higher than that of RPS etching.
Gate-all-around (GAA) nanosheet transistors are widely accepted for the mainstream technology towards 3nm
technology node. The major strategy is to form nanosheet by using Si1-xGex/Si multilayer structures (MLS). Inner spacer
formation is a critical step as it defines the gate length and isolates gate from source and drain. Selectively removing of
SiGe layers determines the dimension of the inner spacer and impacts the transistor performance significantly. It requires
precise process control in the lateral cavity etching and brings significant challenges to conventional etching manners. In
our previous work, we achieved isotropic Si0.7Ge0.3 selective etching in SiGe/Si stack with high selectivity. However, the
results were achieved on the single SiGe/Si stack in a relatively open area, when moving to dense patterns, the etching
performance desires for further study. In this paper, we present our latest progress on isotropic etching by using ICP with
mixed gas of CF4/O2/He on SiGe/Si stack periodic arrays. Loading effect and Si surface damage were observed. We
reproduce these etching effects by developing an analytical model. This model is based on Monte-Carlo method and is
capable of simulating the profile evolution of the lateral etching of SiGe/Si structures. The influence of etch time, pattern
pitch and stack layer thickness on lateral etch results have been studied by simulation.
KEYWORDS: Plasma enhanced chemical vapor deposition, Low pressure chemical vapor deposition, Silicon nitride, Chemical vapor deposition, Nanosheets, Monte Carlo methods, Particles, Modeling, Transistors, Solids
Gate-all-around nanosheet (GAA-NS) transistors are commonly considered to be most competitive logic device in the future. In the GAA nanosheet transistor device fabrication process, the inner spacer formation is a critical step as it physically isolates the gate from the source/drain, and defines the gate length. After the selective lateral etch of the SiGe in alternative Si/SiGe stack, inner spacer material is deposited and SiNx is commonly used. This gap filling process demands for highly uniform growth of materials in order to minimize transistor variability. As moving to three-dimensional stacked structure, lateral open features bring challenges to conventional deposition manners such as chemical vapor deposition (CVD). In our previous work, we have compared the filling performance between low-pressure chemical vapor deposition (LPCVD) and plasma enhanced chemical vapor deposition (PECVD), and demonstrated good SiNx growth conformity by LPCVD in Si/SiGe indentation cavities. The cavity geometry was also found to pose significant impact on growth profile. However these works were carried out on isolated Si/SiGe nanosheet structure without neighboring unit. CVD process performance may degrade when moving from isolated to dense structures, especially when the critical dimension goes into tens of nanometers. In this paper, we present our latest simulation progress on the profile evolution of SiNx CVD in dense Si/SiGe nanosheet structures with varying geometry and density of units. The SiNx profile simulation indicates that LPCVD still maintains promising coverage performance in cavities, the SiNx film thickness in the inner and outer side of unit are pretty close, while necking signature emerges near the unit top as process time increases. In contrast, PECVD exhibits pin holes within the cavity at the beginning of process, and the necking effect is relatively severe both in the cavity and near top of unit. We conduct systematic study on periodic stack structure array with different SiGe indentations. Pin holes are observed and get more pronounced in the PECVD process when the space between units is narrowed down. As the indentation decreases, pin holes become much smaller and exhibit better filling performance inside the lateral cavity.
KEYWORDS: Low pressure chemical vapor deposition, Plasma enhanced chemical vapor deposition, Scanning electron microscopy, Silicon, Ions, Field effect transistors, Transmission electron microscopy, Process modeling, Deposition processes, Computer simulations
The inner spacer process is a critical step in gate-all-around (GAA) nanosheet FET device fabrication and SiN is the most common material to be deposited after the indentation of the SiGe layer of alternative Si/SiGe layer structure. This gap filling process demands for highly uniform growth in order to minimize transistor variability, the lateral open feature of the indentation brings new challenges to conventional deposition technologies such as low-pressure chemical vapor deposition (LPCVD) and plasma enhanced chemical vapor deposition (PECVD). In this work, we propose an analytical model of SiN deposition to predict the profile evolution of both LPCVD and PECVD, which can help process tuning and understand the influence of the multi-layer geometry and process condition on inner spacer growth performance in a more efficient and economical way. Experimental results reveal that the filling effect of LPCVD is significantly better than that of PECVD, simulation results also validate this. We also compare simulations with experiments, by comparing the model output with original SEM image, satisfactory matching between the two profiles demonstrates the validity of this model. Moreover, we set the SiGe layer thickness to be 10nm, 20nm and 30nm, and SiGe indentation as 10nm, 30nm and 50nm. Simulation reveals that the geometry has significant impact on the deposition performance. When the indentation is less than 10nm, both LPCVD and PECVD exhibit good SiN coverage. However, when indentation is deepened from 10nm to 30nm and 50nm, for PECVD, void firstly forms in 10nm thick SiGe layer and the necking effect tends to form larger void in 20nm and 30nm thick SiGe layers. For LPCVD, however, SiN grows more uniformly within and outside the cavity, and only very narrow gaps form in the cavity.
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