Mr. Shaun Dai Profile

Shaun Dai

at ASML Hefei

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Proceedings Article | 26 May 2022 Poster + Paper

New DRAM application space for optical AEI metrology enabled by ASML self reference (ASR) targets

Jimmy Chang, Rui Qin, Junjun Zhang, Wei Zhang, Qian Zhang, Hao Jing, Shaun Dai, Sylvia Yuan, Giacomo Miceli, Bas van den Broek

Proceedings Volume 12053, 120531A (2022) https://doi.org/10.1117/12.2614584

KEYWORDS: Overlay metrology, Semiconducting wafers, Metrology, Etching, Diffractive optical elements, Astronomical imaging, Time metrology, Optical parametric oscillators, Front end of line, Yield improvement

Read Abstract +

The device shrinkage, associated with the latest nodes, comes with tighter overlay budgets. To meet the tighter overlay budgets unconstrained metrology of the device itself is often used to feed the growing complexity of the control loops with dense intra- and inter-field data. ASML’s Self Reference (ASR) In-device metrology has been demonstrated on Front-End-Of-Line (FEOL) and used successfully in High Volume Manufacturing (HVM). In this work we will demonstrate for the first time accurate, robust and reproducible after-etch ASR-based in-device measurement capability for new applications: Active Cut and Storage Node Contact layer. Finding a robust and cost-effective metrology solution is challenging on Active to Active cut, due to low signal strength for any device metrology technology. To be able to measure the overlay of the Active to Active cut currently a special wafer with under-etch is needed, to enhance the contrast. This extra process step and the need for a sacrificial wafer make the approach expensive, difficulty breaking between Critical Dimension Uniformity (CDU) and Overlay, not easier for high order correction and not suitable for HVM. In this work we successfully introduce for the first time the method of ASR-based recipe setup for Active cut layer to remove this extra process step. Middle-End-Of-Line (MEOL) storage node contact layer currently no other after etch measurements are possible at this process step which makes the ASR-based measurement capability even more valuable. The speed and accuracy of this method, combined with an integrated after-development and after-etch control loop, is predicted to bring yield gains over the wafer.

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