Dr. Shih En Tseng Profile

Dr. Shih En Tseng

at ASML Taiwan Ltd

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Author

Publications (13)

Proceedings Article | 1 December 2022 Paper

A study of patterning 36nm-pitch logic contact holes in a metal oxide resist using a high-reflectance phase-shifting mask that results in image reversal

Shih-En Tseng, Chun-Kuang Chen, Dong-Seok Nam, Will Lin, Anthony Yen

Proceedings Volume 12293, 122930C (2022) https://doi.org/10.1117/12.2642302

KEYWORDS: Photomasks, Semiconducting wafers, Calibration, Data modeling, Line width roughness, Logic, Optical lithography, Extreme ultraviolet lithography, Critical dimension metrology, Stochastic processes

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Proceedings Article | 26 May 2022 Presentation + Paper

Computational lithographic study of 0.55 NA EUV single patterning for metal layers for the 2nm logic node and beyond

Weimin Gao, Boer Zhu, Tsann-Bim Chiou, Shih-En Tseng, Will Lin, Chun-Kuang Chen, Joerg Zimmermann, Anthony Yen

Proceedings Volume 12052, 120520G (2022) https://doi.org/10.1117/12.2614225

KEYWORDS: Source mask optimization, Metals, Nanoimprint lithography, Extreme ultraviolet, Photomasks, Logic, Optical lithography, Molybdenum, SRAF, Extreme ultraviolet lithography

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Proceedings Article | 2 April 2020 Presentation + Paper

Simulation investigation of enabling technologies for EUV single exposure of Via patterns in 3nm logic technology

Weimin Gao, Tsann-Bim Chiou, Shih-En Tseng, Pieter Wöltgens, Moyra McManus, Nak Seong, Anthony Yen

Proceedings Volume 11323, 113231L (2020) https://doi.org/10.1117/12.2552888

KEYWORDS: Extreme ultraviolet, Extreme ultraviolet lithography, Logic, Optical lithography, Photomasks, Resolution enhancement technologies, Source mask optimization, Optical proximity correction, Metals, Nanoimprint lithography

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Proceedings Article | 16 October 2017 Presentation + Paper

EUV mask manufacturing readiness in the merchant mask industry

Michael Green, Yohan Choi, Young Ham, Henry Kamberian, Chris Progler, Shih-En Tseng, Tsann-Bim Chiou, Junji Miyazaki, Ad Lammers, Alek Chen

Proceedings Volume 10450, 1045005 (2017) https://doi.org/10.1117/12.2281132

KEYWORDS: Photomasks, SRAF, Extreme ultraviolet, Manufacturing, Optical proximity correction, Extreme ultraviolet lithography, Metals, Inspection, Scanning electron microscopy, Metrology

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As nodes progress into the 7nm and below regime, extreme ultraviolet lithography (EUVL) becomes critical for all industry participants interested in remaining at the leading edge. One key cost driver for EUV in the supply chain is the reflective EUV mask. As of today, the relatively few end users of EUV consist primarily of integrated device manufactures (IDMs) and foundries that have internal (captive) mask manufacturing capability. At the same time, strong and early participation in EUV by the merchant mask industry should bring value to these chip makers, aiding the wide-scale adoption of EUV in the future. For this, merchants need access to high quality, representative test vehicles to develop and validate their own processes. This business circumstance provides the motivation for merchants to form Joint Development Partnerships (JDPs) with IDMs, foundries, Original Equipment Manufacturers (OEMs) and other members of the EUV supplier ecosystem that leverage complementary strengths. In this paper, we will show how, through a collaborative supplier JDP model between a merchant and OEM, a novel, test chip driven strategy is applied to guide and validate mask level process development. We demonstrate how an EUV test vehicle (TV) is generated for mask process characterization in advance of receiving chip maker-specific designs. We utilize the TV to carry out mask process “stress testing” to define process boundary conditions which can be used to create Mask Rule Check (MRC) rules as well as serve as baseline conditions for future process improvement. We utilize Advanced Mask Characterization (AMC) techniques to understand process capability on designs of varying complexity that include EUV OPC models with and without sub-resolution assist features (SRAFs). Through these collaborations, we demonstrate ways to develop EUV processes and reduce implementation risks for eventual mass production. By reducing these risks, we hope to expand access to EUV mask capability for the broadest community possible as the technology is implemented first within and then beyond the initial early adopters.

Proceedings Article | 16 March 2016 Paper

Impact of EUV patterning scenario on different design styles and their ground rules for 7nm/5nm node BEOL layers

Tsann-Bim Chiou, Alek Chen, Mircea Dusa, Shih-En Tseng

Proceedings Volume 9781, 978107 (2016) https://doi.org/10.1117/12.2220019

KEYWORDS: Metals, Extreme ultraviolet, Optical lithography, Back end of line, Line edge roughness, Image processing, Image segmentation, Lithography, Extreme ultraviolet lithography, Printing

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Proceedings Article | 22 April 2011 Paper

MRC optimization for EUV high NA imaging for the 32-nm HP technology node

Shih-En Tseng, Alek Chen

Proceedings Volume 8081, 80810H (2011) https://doi.org/10.1117/12.897221

KEYWORDS: Photomasks, Extreme ultraviolet, Critical dimension metrology, Manufacturing, Lithography, 3D acquisition, Extreme ultraviolet lithography, Mask making, Electroluminescence, Logic

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Proceedings Article | 12 December 2009 Paper

Litho scenario solutions for FinFET SRAM 22nm node

Shih-En Tseng, Shun-Der Wu, Jacques Wang, Jay Kou, Orion Mouraille, Reiner Jungblut, Tsann-Bim Chiou, Jo Finders, Alek Chen, Mircea Dusa, Stephen Hsu

Proceedings Volume 7520, 752025 (2009) https://doi.org/10.1117/12.837495

KEYWORDS: Source mask optimization, Scanners, Photomasks, Reticles, Diffractive optical elements, Double patterning technology, Etching, Lithography, Error analysis

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Proceedings Article | 24 March 2009 Paper

Immersion scanner proximity matching using angle resolving scatterometry metrology

Ren-Jay Kou, Reiner Jungblut, Jan Hauschild, Shih-En Tseng, Jason Shieh, Jim Chen, Alek Chen, Koen Schreel

Proceedings Volume 7272, 727240 (2009) https://doi.org/10.1117/12.816455

KEYWORDS: Scatterometry, Scanners, Metrology, Semiconducting wafers, Optical proximity correction, Systems modeling, Reticles, Lithography, Time metrology, Scatter measurement

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Proceedings Article | 4 December 2008 Paper

Process capability comparison between LELE DPT and spacer for NAND flash 32nm and below

Shih-en Tseng, Alek Chen

Proceedings Volume 7140, 714035 (2008) https://doi.org/10.1117/12.808003

KEYWORDS: Scanners, Photomasks, Reticles, Etching, Semiconducting wafers, Critical dimension metrology, Lithography, Silica, Seaborgium, Imaging devices

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Proceedings Article | 26 March 2007 Paper

The random contact hole solutions for future technology nodes

Alek Chen, Steve Hansen, Marco Moers, Jason Shieh, Andre Engelen, Koen van Ingen Schenau, Shih-en Tseng

Proceedings Volume 6520, 65201B (2007) https://doi.org/10.1117/12.712447

KEYWORDS: Photomasks, Lithography, Extreme ultraviolet, Extreme ultraviolet lithography, Double patterning technology, Logic, Error analysis, Lithographic illumination, Optical lithography, Imaging systems

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Proceedings Article | 20 March 2006 Paper

How to obtain accurate resist simulations in very low-k1 era

Tsann-Bim Chiou, Chan-Ha Park, Jae-Seung Choi, Young-Hong Min, Steve Hansen, Shih-En Tseng, Alek Chen, Donggyu Yim

Proceedings Volume 6154, 61542V (2006) https://doi.org/10.1117/12.658990

KEYWORDS: Calibration, Critical dimension metrology, Photomasks, Data modeling, Scanning electron microscopy, Metrology, Cadmium, Tolerancing, Photoresist processing, Image processing

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A procedure for calibrating a resist model iteratively adjusts appropriate parameters until the simulations of the model match the experimental data. The tunable parameters may include the shape of the illuminator, the geometry and transmittance/phase of the mask, light source and scanner-related parameters that affect imaging quality, resist process control and most importantly the physical/chemical factors in the resist model. The resist model can be accurately calibrated by measuring critical dimensions (CD) of a focus-exposure matrix (FEM) and the technique has been demonstrated to be very successful in predicting lithographic performance. However, resist model calibration is more challenging in the low k1 (<0.3) regime because numerous uncertainties, such as mask and resist CD metrology errors, are becoming too large to be ignored. This study demonstrates a resist model calibration procedure for a 0.29 k1 process using a 6% halftone mask containing 2D brickwall patterns. The influence of different scanning electron microscopes (SEM) and their wafer metrology signal analysis algorithms on the accuracy of the resist model is evaluated. As an example of the metrology issue of the resist pattern, the treatment of a sidewall angle is demonstrated for the resist line ends where the contrast is relatively low. Additionally, the mask optical proximity correction (OPC) and corner rounding are considered in the calibration procedure that is based on captured SEM images. Accordingly, the average root-mean-square (RMS) error, which is the difference between simulated and experimental CDs, can be improved by considering the metrological issues. Moreover, a weighting method and a measured CD tolerance are proposed to handle the different CD variations of the various edge points of the wafer resist pattern. After the weighting method is implemented and the CD selection criteria applied, the RMS error can be further suppressed. Therefore, the resist CD and process window can be confidently evaluated using the accurately calibrated resist model. One of the examples simulates the sensitivity of the mask pattern error, which is helpful to specify the mask CD control.

Proceedings Article | 15 March 2006 Paper

High NA polarized light lithography for 0.29-k1 process

Chanha Park, Jeonkyu Lee, Kiho Yang, Shih-en Tseng, Young-Hong Min, Alek Chen, Hyunjo Yang, Donggyu Yim, Jinwoong Kim

Proceedings Volume 6154, 61540F (2006) https://doi.org/10.1117/12.656841

KEYWORDS: Polarization, Lithography, Line width roughness, Photomasks, Printing, Line edge roughness, Optical lithography, Zirconium, Resolution enhancement technologies, Optical proximity correction

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Proceedings Article | 15 March 2006 Paper

The improvement of DOF for sub-100nm process by focus scan

Jung-Chan Kim, Hyun-Jo Yang, Jin-Hyuck Jeon, Chan-Ha Park, James Moon, Dong-gyu Yim, Jin-Woong Kim, Shih-en Tseng, Kyu-Kab Rhe, Young-Hong Min, Alek Chen

Proceedings Volume 6154, 61541K (2006) https://doi.org/10.1117/12.656897

KEYWORDS: Semiconducting wafers, Electroluminescence, Fiber optic illuminators, Photomasks, Image processing, Overlay metrology, Resolution enhancement technologies, Optical proximity correction, Photoresist processing, Scanners

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Showing 5 of 13 publications

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