At advanced technology nodes (sub-22 nm), design rules become very complicated as interactions between multiple layers become more complex, while the number of design elements within the optical radius increases. As a result, one may possibly encounter novel yield limiters in the 2D/3D design space with every new product taping out to the fab. Key to fast yield ramp is identifying novel constructs that may become yield detractors, and to address the challenge in the DFM space before actual Silicon is run. A comprehensive methodology to find such geometric constructs is proposed.
Optical Proximity Correction (OPC) is a compute-intensive process used to generate photolithography mask shapes at advanced VLSI nodes. Previously, we reported a modified two-step OPC flow which consists of a first pattern replacement step followed by a model based OPC correction step [1]. We build on this previous work and show how this hybrid flow not only improves full chip OPC runtime, but also significantly improves mask correction consistency and overall mask quality. This is demonstrated using a design from the 20nm node, which requires the use of model based SRAF followed by model based OPC to obtain the full mask solution.
KEYWORDS: Statistical analysis, Very large scale integration, Profiling, Data modeling, Databases, Metals, Data mining, Data processing, Data storage, Visualization
Traditional physical design verification tools employ a deck of known design rules, each of which has a pre-defined pass/fail criteria associated with it. While passing a design rule deck is a necessary condition for a VLSI design to be manufacturable, it is not sufficient. Other physical design profiling decks that attempt to obtain statistical information about the various critical dimensions in the VLSI design lack a systematic methodology for rule enumeration. These decks are often inadequate, unable to extract all the interlayer and intralayer dimensions in a design that have a correlation with process yield. The Physical Design Analyzer is a comprehensive design analysis tool built with the objective of exhaustively exploring design-process correlations to increase the wafer yield.
Pattern based design rule checks have emerged as an alternative to the traditional rule based design rule checks in the VLSI verification flow [1]. Typically, the design-process weak-points, also referred as design hotspots, are classified into patterns of fixed size. The size of the pattern defines the radius of influence for the process. These fixed sized patterns are used to search and detect process weak points in new designs without running computationally expensive process simulations. However, both the complexity of the pattern and different kinds of physical processes affect the radii of influence. Therefore, there is a need to determine the optimal pattern radius (size) for efficient hotspot detection. The methodology described here uses a combination of pattern classification and pattern search techniques to create a directed graph, referred to as the Pattern Association Tree (PAT). The pattern association tree is then filtered based on the relevance, sensitivity and context area of each pattern node. The critical patterns are identified by traversing the tree and ranking the patterns. This method has plausible applications in various areas such as process characterization, physical design verification and physical design optimization. Our initial experiments in the area of physical design verification confirm that a pattern deck with the radius optimized for each pattern is significantly more accurate at predicting design hotspots when compared to a conventional deck of fixed sized patterns.
Full chip model based Optical Proximity Correction (OPC) at
advanced nodes involves iteratively modifying the drawn polygon shapes
while simulating them through complex optical and resist models. Due to
the computational complexity of the models and the large size of VLSI
designs, these mask simulations run for very long times. In this study we
propose a pattern replacement step to generate a partial mask solution
before applying model based OPC correction. Since the pattern replacement
step is very fast and model based OPC has to be applied only to a
portion of the design, total mask generation runtime is significantly reduced.
Techniques to control Across Chip CD Variation are very important in IC design, since it directly impacts the electrical timing and
functionality of the designs. VLSI designs today include a rich variety of electrical devices (different gate oxide thicknesses, different
threshold voltages, etc.) to provide the much needed flexibility to the chip designer. These devices occur at different proximities and
different densities on a full chip design. In this paper, we describe a method for improving and ensuring design-to-mask (D2M) quality
via a quantitative relationship between design specification and full chip tapeout results. This is done by applying a layout profiling
technique with the aim of capturing comprehensive representation of the design space, this method ensures the quality of design-to-mask
flow prior to release OPC data to mask house.
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