KEYWORDS: Sum frequency generation, Interfaces, Deep learning, Thin films, Spectroscopy, Signal intensity, Signal attenuation, Polystyrene, Optical surfaces, Vibration
Extreme Ultraviolet Lithography (EUV) and other advanced manufacturing technologies have increased the demand for characterizing 3D integrated structures. Due to the inability to directly access and observe buried interfaces, existing metrology tools face significant challenges in this area. Sum Frequency Generation (SFG) spectroscopy, with its surface and interface selectivity, non-destructive nature, and high sensitivity, represents a feasible option for probing molecular interactions at these buried interfaces. However, the nonlinear characteristics of SFG spectra and the coupling between spectral components make manual spectral decomposition highly complex, requiring extensive experience in spectral analysis and is relatively time-consuming, while the stability can hardly be ensured. This severely limits the application of SFG in large-scale, high-throughput characterizations. To overcome this bottleneck, we have developed a toolkit for the decomposition process by integrating advanced deep learning techniques, specifically a Multi-Layer Perceptron (MLP) network with custom activation functions. This toolkit reduces the analysis time from several hours to just a few minutes, while maintaining high accuracy compared to manual operations.
Directed Self-Assembly (DSA) of cylindrical block copolymer with graphoepitaxy strategy offering significant potential for contact hole multiplication in semiconductor manufacturing at technology nodes below 7 nm (sub-7 nm). This technique allows precise control over the number of DSA-generated holes and their critical dimensions (CD) by manipulating the guiding template geometry and size. The results indicate that DSA quadruple-hole multiplication patterns aligned top-bottom and left-right, with a long-axis spacing of 55-65 nm and a short-axis spacing of 30-40 nm could be achieved through precisely designing template holes with long-axis dimension and short-axis dimension. The formed DSA pattern was successfully transferred to the underlying hard mask layer, creating a large-area quadruple-hole array with a CD of approximately 17 nm. A comprehensive investigation of guiding template size and morphology on multiplication hole patterning enhances the understanding of the self-assembly behavior in confined elliptical spaces. In conclusion, this work highlights the importance of optimizing guiding template size for contact hole multiplication in integrated circuit fabrication.
Directed self-assembly of block copolymer (BCP) has been extensively explored in application of contact hole multiplication at the sub-7 nm technology node. The aim of this study is to investigate the effect of surface affinity on the directed self-assembly of BCP, polystyrene-b-poly (methyl methacrylate) (PS-b-PMMA) for contact hole multiplication. The sidewall affinity of the guiding templates for PS and PMMA blocks is manipulated by controlling the grafting process or the PS mole fraction (fPS) of the brushes, which is favorable for tuning the Center-to-Center Distance (CCD) of the twin-hole pattern. The result demonstrates that the CCD increases with increasing the sidewall affinity for PS block of BCP, which is promising to fabricate high-density hole patterns at the sub-7 nm technology node.
Measurement is a critical aspect of advanced lithography, particularly for evaluating process capabilities in sub-10 nm technology nodes. Traditional manual measurement methods for Scanning Electron Microscopy (SEM) images lack robustness and are inadequate for large-scale analysis, especially for complex 2D features such as dislocations in hexagonal array patterns. To address these limitations, a contour-based algorithm has been developed for measuring Critical Dimension (CD), pitch, and dislocations in hexagonal arrays. By generating virtual layout based on measured CD and pitch, the algorithm enables detailed analysis of placement errors and provides insights into pattern regularity and symmetry. This approach has been verified on SEM images of hexagonal arrays with a pitch of approximately 30 nm, demonstrating its effectiveness in supporting advanced manufacturing process evaluation.
In the sub-7 nm technology nodes, the cost of printing dense via layers increases dramatically. Directed self-assembly (DSA) (DSA) technology with multiple patterning (MP) lithography (DSA-MP) provides a high-volume manufacturing solution with a high throughput and low cost. To enable the technology, a high-quality DSA-MP-aware layout decomposer that contains DSA grouping and MP assignment is necessary. We propose a graph-based heuristic algorithm that minimizes the potential DSA decomposition violations using grouping nodes in the complete graph and the corresponding place-and-route method. Then the grouping result is modified and the MP assignment is solved simultaneously by hybrid algorithms. Experimental results show the efficiency and effectiveness of the proposed method in dealing with large dense vias patterns.
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