A trapezoid (TZOID) pixel array complementary metal oxide semiconductor (CMOS) image sensor, and a pixel-resolution mapping (P-RM) method to extract information from the observed objects without requiring any specific patterns or man-made markings, are proposed for traffic applications. The size of each pixel in the TZOID imager was determined by pixel design equations based on the relationship between the pixel’s physical size and related spatial resolution. The TZOID imager trades detection accuracy for a tolerable data loss to reduce communication bandwidth and computation power. The P-RM method determines the pixels’ actual resolutions in the real world of the captured imaged by both standard rectangular single- and multiresolution TZOID pixel arrays. Both indoor and outdoor experiments were performed using single- and multiresolution imagers. The TZOID imager integrated circuit (IC) was fabricated in a 0.18-μm CMOS process. It was tested, and its performance parameters were compared with an off-the-shelf CMOS image sensor IC. Tests showed that the TZOID generates 98% less data than that of a standard image sensor, trading off only 2% detection accuracy. Results also show that the proposed method provides a general procedure for designing a multiresolution sensor for traffic applications.
A 512×512 CMOS Active Pixel Sensor (APS) imager has been designed, fabricate, and tested for frontside illumination suitable for use in astronomy specifically in telescope guider systems as a replacement of CCD chips. The imager features a high-speed differential analog readout, 15 μm pixel pitch, 75 % fill factor (FF), 62 dB dynamic range, 315Ke- pixel capacity, less than 0.25% fixed pattern noise (FPN), 45 dB signal to noise ratio (SNR) and frame rate of up to 40 FPS. Design was implemented in a standard 0.5 μm CMOS process technology consuming less than 200mWatts on a single 5 Volt power supply.
CMOS Active Pixel Sensor (APS) imager was developed with pixel structure suitable for both frontside and backside illumination holding large number of electron in relatively small pixel pitch of 15 μm. High-speed readout and signal processing circuits were designed to achieve low fixed pattern noise (FPN) and non-uniformity to provide CCD-like analog outputs. Target spectrum range of operation for the imager is in near ultraviolet (300-400 nm) with high quantum efficiency. This device is going to be used as a test vehicle to develop backside-thinning process.
The Optically Programmable Gate Array (OPGA), an optical version of a conventional FPGA, benefits from a direct parallel interface between an optical memory and a logic circuit. The OPGA utilizes a holographic memory accessed by an array of VCSELs to program its logic. An active pixel sensor array incorporated into the OPGA chip makes it possible to optically address the logic in a very short time allowing for rapid dynamic reconfiguration. Combining spatial and shift multiplexing to store the configuration pages in the memory, the OPGA module can be made compact. The reconfiguration capability of the OPGA can be applied to solve more efficiently problems in pattern recognition and database search.
Reconfigurable processors bring a new computational paradigm where the processor modifies its structure to suit a given application, rather than having to modify the application to fit the device. The Optically Programmable Gate Array, an enhanced version of a conventional FPGA, utilizes a holographic memory accessed by an array of VCSELs to program its logic. Combining spatial and shift multipexing to store the configuration pages in the memory, the OPGA module is very compact and has extremely short configuration time allowing for dynamic reconfiguration. The reconfiguration capability of the OPGA can be applied to solve more efficiently problems in pattern recognition and digit classification.
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